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/rk3399_ARM-atf/include/lib/
H A Dmmio.h34 uint16_t set) in mmio_clrsetbits_16() argument
36 mmio_write_16(addr, (mmio_read_16(addr) & ~clear) | set); in mmio_clrsetbits_16()
64 static inline void mmio_setbits_32(uintptr_t addr, uint32_t set) in mmio_setbits_32() argument
66 mmio_write_32(addr, mmio_read_32(addr) | set); in mmio_setbits_32()
71 uint32_t set) in mmio_clrsetbits_32() argument
73 mmio_write_32(addr, (mmio_read_32(addr) & ~clear) | set); in mmio_clrsetbits_32()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c36 } set[NR_PMIC_WRAP_PHASE]; member
52 .set[PMIC_WRAP_PHASE_ALLINONE] = {
72 .set[PMIC_WRAP_PHASE_ALLINONE] = {
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
143 if (pw == NULL || idx >= pw->set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
147 pw->set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
151 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
161 (pw != NULL && idx < pw->set[phase].nr_idx)) { in mt_spm_pmic_wrap_get_cmd()
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c49 } set[NR_PMIC_WRAP_PHASE]; member
55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
158 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c54 } set[NR_PMIC_WRAP_PHASE]; member
60 .set[PMIC_WRAP_PHASE_ALLINONE] = {
120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
123 (pw.set[phase]._[idx].cmd_wdata)); in mt_spm_pmic_wrap_set_phase()
131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_set_cmd()
135 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
140 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | cmd_wdata); in mt_spm_pmic_wrap_set_cmd()
147 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_get_cmd()
151 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c49 } set[NR_PMIC_WRAP_PHASE]; member
55 .set[PMIC_WRAP_PHASE_ALLINONE] = {
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
135 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_set_cmd()
139 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
143 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
154 if (idx >= pw.set[phase].nr_idx) { in mt_spm_pmic_wrap_get_cmd()
158 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/include/
H A Drk3399_mcu.h20 #define mmio_setbits_32(addr, set) \ argument
21 mmio_write_32(addr, (mmio_read_32(addr)) | (set))
22 #define mmio_clrsetbits_32(addr, clear, set) \ argument
23 mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c52 } set[NR_PMIC_WRAP_PHASE]; member
58 .set[PMIC_WRAP_PHASE_ALLINONE] = {
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
147 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
150 pw.set[phase]._[idx].cmd_wdata = cmd_wdata; in mt_spm_pmic_wrap_set_cmd()
155 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_cmd()
165 if (idx >= pw.set[phase].nr_idx) in mt_spm_pmic_wrap_get_cmd()
168 return pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_get_cmd()
/rk3399_ARM-atf/include/drivers/nxp/dcfg/
H A Dscfg.h51 #define scfg_clrsetbits32(a, clear, set) \ argument
52 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
58 #define scfg_clrsetbits32(a, clear, set) \ argument
59 mmio_clrsetbits_32((uintptr_t)(a), clear, set)
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm.c96 static void spm_ap_mdsrc_req(int set) in spm_ap_mdsrc_req() argument
100 if (set) in spm_ap_mdsrc_req()
127 static void spm_ap_gpueb_pll_control(int set) in spm_ap_gpueb_pll_control() argument
131 if (set) in spm_ap_gpueb_pll_control()
255 int mt_spm_hwctrl(uint32_t type, int set, void *priv) in mt_spm_hwctrl() argument
261 spm_ap_mdsrc_req(set); in mt_spm_hwctrl()
275 spm_ap_gpueb_pll_control(set); in mt_spm_hwctrl()
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-internals.rst13 Default is 0 (disabled). This option will be set to 1 (enabled) when ``SPD=spmd``
14 and ``SPMD_SPM_AT_SEL2`` is set or when ``ENABLE_RME`` is set to 1 (enabled).
18 ELs which gets trapped in EL3. This option will be set to 1 (enabled) if
19 ``HANDLE_EA_EL3_FIRST_NS`` is set. Currently only NS world routes EA to EL3 but
/rk3399_ARM-atf/docs/process/
H A Dfaq.rst7 Often it is necessary to update your patch set before it is merged. Refer to the
10 If you need to modify an existing patch set with multiple commits, refer to the
18 * How important the patch set is considered by the TF maintainers. Where
20 set and the impact of any delay. Feel free to add a comment to your patch set
23 * The quality of the patch set. Patches are likely to be merged more quickly if
27 * The impact of the patch set. For example, a patch that changes a key generic
63 ``integration`` or another patch set, rather than ``master``. There is a risk
64 that the dependency commits will change (for example due to patch set rework or
80 …et documentation: https://review.trustedfirmware.org/Documentation/intro-user.html#upload-patch-set
/rk3399_ARM-atf/docs/components/spd/
H A Dtrusty-dispatcher.rst4 Trusty is a a set of software components, supporting a Trusted Execution
21 If this function is provided ``args->arg0`` must be set to the memory
25 can be set to a platform specific parameter block, and ``args->arg2``
26 should then be set to the size of that block.
/rk3399_ARM-atf/plat/nxp/soc-ls1043a/
H A Dsoc.def17 # set to GIC400 or GIC500
20 # set to CCI400 or CCN504 or CCN508
23 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
37 # ddr controller - set to MMDC or NXP
40 # ddr phy - set to NXP or SNPS
/rk3399_ARM-atf/plat/nxp/soc-ls1046a/
H A Dsoc.def17 # set to GIC400 or GIC500
20 # set to CCI400 or CCN504 or CCN508
23 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
37 # ddr controller - set to MMDC or NXP
40 # ddr phy - set to NXP or SNPS
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm.c98 static void spm_ap_mdsrc_req(int set) in spm_ap_mdsrc_req() argument
102 if (set) in spm_ap_mdsrc_req()
130 static void spm_ap_gpueb_pll_control(int set) in spm_ap_gpueb_pll_control() argument
134 if (set) in spm_ap_gpueb_pll_control()
267 int mt_spm_hwctrl(uint32_t type, int set, void *priv) in mt_spm_hwctrl() argument
272 spm_ap_mdsrc_req(set); in mt_spm_hwctrl()
282 spm_ap_gpueb_pll_control(set); in mt_spm_hwctrl()
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.h138 #define mmio_clrsetbits32(addr, clear, set) mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (… argument
140 #define mmio_setbits32(addr, set) mmio_write_32(addr, mmio_read_32(addr) | (set)) argument
/rk3399_ARM-atf/plat/mediatek/include/lpm_v2/
H A Dmt_lp_rm.h60 int (*hwctrl)(unsigned int type, int set, void *priv);
75 extern int mt_lp_rm_do_hwctrl(unsigned int type, int set, void *priv);
/rk3399_ARM-atf/plat/socionext/synquacer/drivers/scpi/
H A Dsq_scpi.c134 cmd->set = SCPI_SET_NORMAL; in scpi_set_sq_power_state()
160 cmd->set = 0; in scpi_sys_power_state()
189 cmd->set = SCPI_SET_EXTENDED; in scpi_get_draminfo()
/rk3399_ARM-atf/plat/arm/board/morello/fdts/
H A Dmorello_nt_fw_config.dts14 * The values will be set to the correct values during
29 * The value will be set to the correct values during
/rk3399_ARM-atf/docs/perf/
H A Dperformance-monitoring-unit.rst79 - If set to ``0``, will increment the associated ``PMEVCNTR<n>`` at EL1.
91 - If set to ``1``, will increment the associated ``PMEVCNTR<n>`` at EL2.
127 - If set to ``1`` enables the cycle counter ``PMCCNTR``.
134 - If set to ``1`` it disables the cycle counter ``PMCCNTR`` where event
137 - If set to ``0``, ``PMCCNTR`` will not be affected by this bit and
/rk3399_ARM-atf/docs/components/
H A Dactivity-monitors.rst7 through a set of 64-bit counters.
18 FEAT_AMUv1 describes a set of implementation-defined auxiliary counters (also
H A Dplatform-interrupt-controller-API.rst117 This API should set the priority of the interrupt specified by first parameter
118 ``id`` to the value set by the second parameter ``priority``.
121 writes to GIC *Priority Register* set interrupt priority.
167 This API should set the interrupt specified by first parameter ``id`` to the
193 - When the build option ``GICV2_G0_FOR_EL3`` is set to ``0`` (the default),
224 This API should set the routing mode of Share Peripheral Interrupt (SPI)
237 writes to the GIC *Target Register* (GICv2) or *Route Register* (GICv3) to set
248 This API should set the interrupt specified by first parameter ``id`` to
253 and writes to the GIC *Set Pending Register* to set the interrupt pending
279 This API should set the priority mask (first parameter) in the interrupt
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-5.rst32 bit is set to zero, the cycle counter (when enabled) counts during secure world
36 normal and secure worlds, normal world code can set ``PMCR_EL0.DP`` to zero to
43 some implementations, ``PMCR_EL0.DP`` is set to zero by default. This and other
/rk3399_ARM-atf/plat/nxp/soc-lx2160a/
H A Dsoc.def18 # set to GIC400 or GIC500
21 # set to CCI400 or CCN504 or CCN508
24 # indicate layerscape chassis level - set to 3=LSCH3 or 2=LSCH2
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_scpi.c153 cmd->set = SCPI_SET_NORMAL; in scpi_set_brcm_power_state()
241 cmd->set = 0; in scpi_sys_power_state()

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