xref: /rk3399_ARM-atf/plat/mediatek/include/lpm_v2/mt_lp_rm.h (revision cf2df874cd09305ac7282fadb0fef6be597dfffb)
1*da8cc41bSWenzhen Yu /*
2*da8cc41bSWenzhen Yu  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*da8cc41bSWenzhen Yu  *
4*da8cc41bSWenzhen Yu  * SPDX-License-Identifier: BSD-3-Clause
5*da8cc41bSWenzhen Yu  */
6*da8cc41bSWenzhen Yu 
7*da8cc41bSWenzhen Yu #ifndef MT_LP_RM_H
8*da8cc41bSWenzhen Yu #define MT_LP_RM_H
9*da8cc41bSWenzhen Yu 
10*da8cc41bSWenzhen Yu #include <stdbool.h>
11*da8cc41bSWenzhen Yu 
12*da8cc41bSWenzhen Yu #define MT_RM_STATUS_OK		0
13*da8cc41bSWenzhen Yu #define MT_RM_STATUS_BAD	-1
14*da8cc41bSWenzhen Yu #define MT_RM_STATUS_STOP	-2
15*da8cc41bSWenzhen Yu 
16*da8cc41bSWenzhen Yu enum plat_mt_lpm_rc_type {
17*da8cc41bSWenzhen Yu 	PLAT_RC_UPDATE_CONDITION,
18*da8cc41bSWenzhen Yu 	PLAT_RC_STATUS,
19*da8cc41bSWenzhen Yu 	PLAT_RC_UPDATE_REMAIN_IRQS,
20*da8cc41bSWenzhen Yu 	PLAT_RC_IS_FMAUDIO,
21*da8cc41bSWenzhen Yu 	PLAT_RC_IS_ADSP,
22*da8cc41bSWenzhen Yu 	PLAT_RC_ENTER_CNT,
23*da8cc41bSWenzhen Yu 	PLAT_RC_CLKBUF_STATUS,
24*da8cc41bSWenzhen Yu 	PLAT_RC_UFS_STATUS,
25*da8cc41bSWenzhen Yu 	PLAT_RC_IS_USB_PERI,
26*da8cc41bSWenzhen Yu 	PLAT_RC_IS_USB_INFRA,
27*da8cc41bSWenzhen Yu 	PLAT_RC_IS_USB_HEADSET,
28*da8cc41bSWenzhen Yu 	PLAT_RC_MAX,
29*da8cc41bSWenzhen Yu };
30*da8cc41bSWenzhen Yu 
31*da8cc41bSWenzhen Yu enum plat_mt_lpm_hw_ctrl_type {
32*da8cc41bSWenzhen Yu 	PLAT_AP_MDSRC_REQ,
33*da8cc41bSWenzhen Yu 	PLAT_AP_MDSRC_ACK,
34*da8cc41bSWenzhen Yu 	PLAT_AP_IS_MD_SLEEP,
35*da8cc41bSWenzhen Yu 	PLAT_AP_MDSRC_SETTLE,
36*da8cc41bSWenzhen Yu 	PLAT_AP_GPUEB_PLL_CONTROL,
37*da8cc41bSWenzhen Yu 	PLAT_AP_GPUEB_PWR_STATUS,
38*da8cc41bSWenzhen Yu 	PLAT_AP_GPUEB_MFG0_PWR_CON,
39*da8cc41bSWenzhen Yu 	PLAT_AP_ASSERT_SPM_IRQ,
40*da8cc41bSWenzhen Yu 	PLAT_AP_SPM_RESOURCE_REQUEST_UPDATE,
41*da8cc41bSWenzhen Yu 	PLAT_AP_SPM_WDT_TRIGGER,
42*da8cc41bSWenzhen Yu 	PLAT_AP_HW_CTRL_MAX,
43*da8cc41bSWenzhen Yu };
44*da8cc41bSWenzhen Yu 
45*da8cc41bSWenzhen Yu struct mt_resource_constraint {
46*da8cc41bSWenzhen Yu 	int level;
47*da8cc41bSWenzhen Yu 	int (*init)(void);
48*da8cc41bSWenzhen Yu 	bool (*is_valid)(unsigned int cpu, int stateid);
49*da8cc41bSWenzhen Yu 	int (*update)(int stateid, int type, const void *p);
50*da8cc41bSWenzhen Yu 	int (*run)(unsigned int cpu, int stateid);
51*da8cc41bSWenzhen Yu 	int (*reset)(unsigned int cpu, int stateid);
52*da8cc41bSWenzhen Yu 	int (*get_status)(unsigned int type, void *priv);
53*da8cc41bSWenzhen Yu 	unsigned int (*allow)(int stateid);
54*da8cc41bSWenzhen Yu };
55*da8cc41bSWenzhen Yu 
56*da8cc41bSWenzhen Yu struct mt_resource_manager {
57*da8cc41bSWenzhen Yu 	int (*update)(struct mt_resource_constraint **con, unsigned int num,
58*da8cc41bSWenzhen Yu 		      int stateid, void *priv);
59*da8cc41bSWenzhen Yu 	struct mt_resource_constraint **consts;
60*da8cc41bSWenzhen Yu 	int (*hwctrl)(unsigned int type, int set, void *priv);
61*da8cc41bSWenzhen Yu };
62*da8cc41bSWenzhen Yu 
63*da8cc41bSWenzhen Yu extern int mt_lp_rm_register(struct mt_resource_manager *rm);
64*da8cc41bSWenzhen Yu extern int mt_lp_rm_do_constraint(unsigned int constraint_id,
65*da8cc41bSWenzhen Yu 				  unsigned int cpuid, int stateid);
66*da8cc41bSWenzhen Yu extern int mt_lp_rm_find_constraint(unsigned int idx, unsigned int cpuid,
67*da8cc41bSWenzhen Yu 				    int stateid, void *priv);
68*da8cc41bSWenzhen Yu extern int mt_lp_rm_find_and_run_constraint(unsigned int idx,
69*da8cc41bSWenzhen Yu 					    unsigned int cpuid,
70*da8cc41bSWenzhen Yu 					    int stateid, void *priv);
71*da8cc41bSWenzhen Yu extern int mt_lp_rm_reset_constraint(unsigned int idx,
72*da8cc41bSWenzhen Yu 				     unsigned int cpuid, int stateid);
73*da8cc41bSWenzhen Yu extern int mt_lp_rm_do_update(int stateid, int type, void const *p);
74*da8cc41bSWenzhen Yu extern int mt_lp_rm_get_status(unsigned int type, void *priv);
75*da8cc41bSWenzhen Yu extern int mt_lp_rm_do_hwctrl(unsigned int type, int set, void *priv);
76*da8cc41bSWenzhen Yu 
77*da8cc41bSWenzhen Yu #endif /* MT_LP_RM_H */
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