1050a99a6SPankaj Gupta /* 2050a99a6SPankaj Gupta * Copyright 2020-2021 NXP 3050a99a6SPankaj Gupta * 4050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5050a99a6SPankaj Gupta * 6050a99a6SPankaj Gupta */ 7050a99a6SPankaj Gupta 8050a99a6SPankaj Gupta #ifndef SCFG_H 9050a99a6SPankaj Gupta #define SCFG_H 10050a99a6SPankaj Gupta 11050a99a6SPankaj Gupta #ifdef CONFIG_CHASSIS_2 12050a99a6SPankaj Gupta 13050a99a6SPankaj Gupta /* SCFG register offsets */ 14050a99a6SPankaj Gupta #define SCFG_CORE0_SFT_RST_OFFSET 0x0130 15050a99a6SPankaj Gupta #define SCFG_SNPCNFGCR_OFFSET 0x01A4 16050a99a6SPankaj Gupta #define SCFG_CORESRENCR_OFFSET 0x0204 17050a99a6SPankaj Gupta #define SCFG_RVBAR0_0_OFFSET 0x0220 18050a99a6SPankaj Gupta #define SCFG_RVBAR0_1_OFFSET 0x0224 19050a99a6SPankaj Gupta #define SCFG_COREBCR_OFFSET 0x0680 20050a99a6SPankaj Gupta #define SCFG_RETREQCR_OFFSET 0x0424 21050a99a6SPankaj Gupta 22050a99a6SPankaj Gupta #define SCFG_COREPMCR_OFFSET 0x042C 23050a99a6SPankaj Gupta #define COREPMCR_WFIL2 0x1 24050a99a6SPankaj Gupta 25050a99a6SPankaj Gupta #define SCFG_GIC400_ADDR_ALIGN_OFFSET 0x0188 26050a99a6SPankaj Gupta #define SCFG_BOOTLOCPTRH_OFFSET 0x0600 27050a99a6SPankaj Gupta #define SCFG_BOOTLOCPTRL_OFFSET 0x0604 28050a99a6SPankaj Gupta #define SCFG_SCRATCHRW2_OFFSET 0x0608 29050a99a6SPankaj Gupta #define SCFG_SCRATCHRW3_OFFSET 0x060C 30050a99a6SPankaj Gupta 31050a99a6SPankaj Gupta /* SCFG bit fields */ 32050a99a6SPankaj Gupta #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 33050a99a6SPankaj Gupta #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 34*3a8c9d78SJiafei Pan 35*3a8c9d78SJiafei Pan /* GIC Address Align Register */ 36*3a8c9d78SJiafei Pan #define SCFG_GIC400_ADDR_ALIGN_4KMODE_MASK 0x80000000 37*3a8c9d78SJiafei Pan #define SCFG_GIC400_ADDR_ALIGN_4KMODE_EN 0x80000000 38*3a8c9d78SJiafei Pan #define SCFG_GIC400_ADDR_ALIGN_4KMODE_DIS 0x0 39*3a8c9d78SJiafei Pan 40050a99a6SPankaj Gupta #endif /* CONFIG_CHASSIS_2 */ 41050a99a6SPankaj Gupta 42050a99a6SPankaj Gupta #ifndef __ASSEMBLER__ 43050a99a6SPankaj Gupta #include <endian.h> 44050a99a6SPankaj Gupta #include <lib/mmio.h> 45050a99a6SPankaj Gupta 46050a99a6SPankaj Gupta #ifdef NXP_SCFG_BE 47050a99a6SPankaj Gupta #define scfg_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 48050a99a6SPankaj Gupta #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 49050a99a6SPankaj Gupta #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 50050a99a6SPankaj Gupta #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 51050a99a6SPankaj Gupta #define scfg_clrsetbits32(a, clear, set) \ 52050a99a6SPankaj Gupta mmio_clrsetbits_32((uintptr_t)(a), clear, set) 53fb90cfd4SJiafei Pan #elif defined(NXP_SCFG_LE) 54050a99a6SPankaj Gupta #define scfg_in32(a) mmio_read_32((uintptr_t)(a)) 55050a99a6SPankaj Gupta #define scfg_out32(a, v) mmio_write_32((uintptr_t)(a), v) 56050a99a6SPankaj Gupta #define scfg_setbits32(a, v) mmio_setbits_32((uintptr_t)(a), v) 57050a99a6SPankaj Gupta #define scfg_clrbits32(a, v) mmio_clrbits_32((uintptr_t)(a), v) 58050a99a6SPankaj Gupta #define scfg_clrsetbits32(a, clear, set) \ 59050a99a6SPankaj Gupta mmio_clrsetbits_32((uintptr_t)(a), clear, set) 60050a99a6SPankaj Gupta #else 61050a99a6SPankaj Gupta #error Please define CCSR SCFG register endianness 62050a99a6SPankaj Gupta #endif 63050a99a6SPankaj Gupta #endif /* __ASSEMBLER__ */ 64050a99a6SPankaj Gupta 65050a99a6SPankaj Gupta #endif /* SCFG_H */ 66