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Searched refs:phase (Results 1 – 25 of 27) sorted by relevance

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/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/v1/
H A Dmt_spm_pmic_wrap.c17 int mt_spm_pmic_wrap_set_phase(unsigned int phase) in mt_spm_pmic_wrap_set_phase() argument
26 if (phase >= pmic_wrap->phase_nr_idx) in mt_spm_pmic_wrap_set_phase()
29 current_phase = &pmic_wrap->phase[phase]; in mt_spm_pmic_wrap_set_phase()
41 int mt_spm_pmic_wrap_set_cmd(unsigned int phase, in mt_spm_pmic_wrap_set_cmd() argument
50 if (phase >= pmic_wrap->phase_nr_idx) in mt_spm_pmic_wrap_set_cmd()
53 if (idx >= pmic_wrap->phase[phase].nr_idx) in mt_spm_pmic_wrap_set_cmd()
56 current_phase = &pmic_wrap->phase[phase]; in mt_spm_pmic_wrap_set_cmd()
65 unsigned long mt_spm_pmic_wrap_get_cmd(unsigned int phase, unsigned int idx) in mt_spm_pmic_wrap_get_cmd() argument
70 if (phase >= pmic_wrap->phase_nr_idx) in mt_spm_pmic_wrap_get_cmd()
73 if (idx >= pmic_wrap->phase[phase].nr_idx) in mt_spm_pmic_wrap_get_cmd()
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/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_pmic_wrap.c28 enum pmic_wrap_phase_id phase; member
50 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
70 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
111 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) in mt_spm_pmic_wrap_set_phase() argument
115 if (phase < NR_PMIC_WRAP_PHASE) { in mt_spm_pmic_wrap_set_phase()
120 if (pw->phase != phase) { in mt_spm_pmic_wrap_set_phase()
121 pw->phase = phase; in mt_spm_pmic_wrap_set_phase()
125 for (idx = 0; idx < pw->set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
126 addr = pw->set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
127 data = pw->set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
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H A Dmt_spm_pmic_wrap.h33 extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
34 extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
36 extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_pmic_wrap.c41 enum pmic_wrap_phase_id phase; member
53 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
100 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) in mt_spm_pmic_wrap_set_phase() argument
104 if (phase >= NR_PMIC_WRAP_PHASE) { in mt_spm_pmic_wrap_set_phase()
108 if (pw.phase == phase) { in mt_spm_pmic_wrap_set_phase()
116 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
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H A Dmt_spm_pmic_wrap.h40 extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
41 extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
43 extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_pmic_wrap.c46 enum pmic_wrap_phase_id phase; member
58 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
105 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) in mt_spm_pmic_wrap_set_phase() argument
109 if ((phase >= NR_PMIC_WRAP_PHASE) || (pw.phase == phase)) { in mt_spm_pmic_wrap_set_phase()
117 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
120 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
122 (pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT) | in mt_spm_pmic_wrap_set_phase()
123 (pw.set[phase]._[idx].cmd_wdata)); in mt_spm_pmic_wrap_set_phase()
127 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx, in mt_spm_pmic_wrap_set_cmd() argument
131 if ((phase >= NR_PMIC_WRAP_PHASE) || (idx >= pw.set[phase].nr_idx)) { in mt_spm_pmic_wrap_set_cmd()
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H A Dmt_spm_pmic_wrap.h41 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
42 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, unsigned int idx,
44 uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, unsigned int idx);
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_pmic_wrap.c41 enum pmic_wrap_phase_id phase; member
53 .phase = NR_PMIC_WRAP_PHASE, /* invalid setting for init */
100 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) in mt_spm_pmic_wrap_set_phase() argument
104 if (phase >= NR_PMIC_WRAP_PHASE) { in mt_spm_pmic_wrap_set_phase()
108 if (pw.phase == phase) { in mt_spm_pmic_wrap_set_phase()
116 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
119 for (idx = 0U; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
120 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
121 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
126 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
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H A Dmt_spm_pmic_wrap.h40 extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
41 extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
43 extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase,
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm_pmic_wrap.c44 enum pmic_wrap_phase_id phase; member
56 .phase = NR_PMIC_WRAP_PHASE,
115 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase) in mt_spm_pmic_wrap_set_phase() argument
119 if (phase >= NR_PMIC_WRAP_PHASE) in mt_spm_pmic_wrap_set_phase()
122 if (pw.phase == phase) in mt_spm_pmic_wrap_set_phase()
128 pw.phase = phase; in mt_spm_pmic_wrap_set_phase()
132 for (idx = 0; idx < pw.set[phase].nr_idx; idx++) { in mt_spm_pmic_wrap_set_phase()
133 addr = pw.set[phase]._[idx].cmd_addr << SPM_DATA_SHIFT; in mt_spm_pmic_wrap_set_phase()
134 data = pw.set[phase]._[idx].cmd_wdata; in mt_spm_pmic_wrap_set_phase()
139 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, uint32_t idx, in mt_spm_pmic_wrap_set_cmd() argument
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H A Dspm_pmic_wrap.h45 void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase);
46 void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase,
48 uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, uint32_t idx);
/rk3399_ARM-atf/plat/st/common/
H A Dstm32cubeprogrammer_usb.c20 uint8_t phase; member
36 if (dfu->phase != PHASE_RESET) { \
40 dfu->phase = PHASE_RESET; \
65 dfu->buffer[0] = dfu->phase; in dfu_callback_upload()
75 if (dfu->phase == PHASE_FLASHLAYOUT && in dfu_callback_upload()
80 if (dfu->phase == PHASE_RESET) { in dfu_callback_upload()
90 dfu->phase, alt, usb_dfu_get_phase(alt)); in dfu_callback_upload()
108 if ((dfu->phase != usb_dfu_get_phase(alt)) || in dfu_callback_download()
111 dfu->phase, alt, (uint32_t)dfu->address); in dfu_callback_download()
130 if (dfu->phase != usb_dfu_get_phase(alt)) { in dfu_callback_manifestation()
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H A Dstm32cubeprogrammer_uart.c60 uint8_t phase; member
69 if (handle.phase != PHASE_RESET) { \
71 handle.phase = PHASE_RESET; \
230 if (handle.phase == PHASE_RESET) { in uart_send_phase()
239 ret = uart_write_8(handle.phase); in uart_send_phase()
387 start_address, handle.phase); in uart_start_cmd()
393 buffer, handle.phase); in uart_start_cmd()
407 handle.phase = id; in uart_read()
450 if ((ret == 0) && (handle.phase == PHASE_RESET)) { in uart_read()
462 if ((ret == 0) && (handle.phase == id)) { in uart_read()
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H A Dbl2_io_storage.c415 static void stm32cubeprogrammer_uart(uint8_t phase, uintptr_t base, size_t len) in stm32cubeprogrammer_uart() argument
423 ret = stm32cubeprog_uart_load(uart_base, phase, base, len); in stm32cubeprogrammer_uart()
429 static void stm32cubeprogrammer_usb(uint8_t phase, uintptr_t base, size_t len) in stm32cubeprogrammer_usb() argument
439 ret = stm32cubeprog_usb_load(pdev, phase, base, len); in stm32cubeprogrammer_usb()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/version/pmic_wrap/inc/
H A Dmt_spm_pmic_wrap.h22 struct pmic_wrap_phase_setting *phase; member
26 int mt_spm_pmic_wrap_set_phase(unsigned int phase);
27 int mt_spm_pmic_wrap_set_cmd(unsigned int phase,
29 unsigned long mt_spm_pmic_wrap_get_cmd(unsigned int phase, unsigned int idx);
/rk3399_ARM-atf/plat/st/common/include/
H A Dstm32cubeprogrammer.h25 uint8_t phase,
29 int stm32cubeprog_uart_load(uintptr_t instance, uint8_t phase,
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_plat_spm_setting.c82 .phase = phase_table,
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/
H A Drse_measured_boot_flow.puml19 == RSE Boot phase ==
54 == RSE Runtime / AP Boot phase ==
H A Drse_attestation_flow.puml15 == RMM Boot phase ==
/rk3399_ARM-atf/docs/design_documents/
H A Dcmake_framework.rst104 In the provisioning phase, first we have to obtain the necessary resources, i.e.
108 In the development phase first we run CMake, which will generate the buildsystem
114 Usually during development only the steps in this second phase have to be
115 repeated, while the provisioning phase needs to be done only once (or rarely).
H A Drse.rst109 current use case only requires message exchange during the boot phase. In
110 the boot phase, only a single core is running and the rest of the cores are
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_plat_spm_setting.c224 .phase = phase_table,
/rk3399_ARM-atf/docs/design/
H A Dinterrupt-framework-design.rst521 service at runtime during its initialisation phase.
537 service during the registration phase. The SPD service would also need to
541 registration phase if it is not known to the SPD service at build time.
565 registration phase.
915 time or during the registration phase. Before handling the interrupt, the SP
/rk3399_ARM-atf/docs/components/
H A Drmm-el3-comms-spec.rst118 utilizing this buffer during the boot phase, prior to return back to EL3 via
221 services during the boot phase as well. The EL3 runtime service handling must
995 be freed again, and they must happen during the cold/warm boot phase of RMM.
/rk3399_ARM-atf/docs/about/
H A Dlts.rst115 taking into account the test-and-debug phase before LTS is cut (see below) --

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