1 /*
2 * Copyright (c) 2025, Mediatek Inc. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdbool.h>
8
9 #include <lib/mmio.h>
10 #include <platform_def.h>
11
12 #include <mt_plat_spm_setting.h>
13 #include <mt_spm.h>
14 #include <mt_spm_internal.h>
15 #include <mt_spm_reg.h>
16 #include <pmic_wrap/inc/mt_spm_pmic_wrap.h>
17
18 /*
19 * BIT Operation
20 */
21 #define CMD_DATA(h, l, v) ((GENMASK(h, l) & ((v) << (l))))
22 #define VOLT_DATA(v) CMD_DATA(7, 0, VOLT_TO_PMIC_VAL(v))
23 /*
24 * PMIC_WRAP
25 */
26 #define VCORE_BASE_UV 0 /* PMIC MT6316 */
27 #define VOLT_TO_PMIC_VAL(volt) (((volt) - VCORE_BASE_UV + 500 - 1) / 500)
28 #define PMIC_VAL_TO_VOLT(pmic) (((pmic) * 500) + VCORE_BASE_UV)
29
30 #define NR_PMIC_WRAP_CMD NR_IDX_ALL
31 #define MAX_RETRY_COUNT 100
32 #define SPM_DATA_SHIFT 16
33
34 /* MT6316 */
35 #define MT6316_TOP_VRCTL_VOSEL_VBUCK1 0x1448
36 #define MT6316_VCORE_VBUCK1_ON 0x1441
37 #define MT6316_VCORE_VBUCK1_OFF 0x1442
38
39 static struct pmic_wrap_cmd_setting cmd_table[NR_PMIC_WRAP_CMD] = {
40 {SPM_PWRAP_CMD0, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(57500)},
41 {SPM_PWRAP_CMD1, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(57500)},
42 {SPM_PWRAP_CMD2, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(60000)},
43 {SPM_PWRAP_CMD3, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(65000)},
44 {SPM_PWRAP_CMD4, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(72500)},
45 {SPM_PWRAP_CMD5, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(72500)},
46 {SPM_PWRAP_CMD6, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(82500)},
47 {SPM_PWRAP_CMD7, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(87500)},
48 {SPM_PWRAP_CMD8, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(87500)},
49 {SPM_PWRAP_CMD9, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(57500)},
50 {SPM_PWRAP_CMD10, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(60000)},
51 {SPM_PWRAP_CMD11, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(65000)},
52 {SPM_PWRAP_CMD12, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(72500)},
53 {SPM_PWRAP_CMD13, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(82500)},
54 {SPM_PWRAP_CMD14, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(87500)},
55 {SPM_PWRAP_CMD15, MT6316_VCORE_VBUCK1_ON, 1},
56 {SPM_PWRAP_CMD16, MT6316_VCORE_VBUCK1_OFF, 1},
57 {SPM_PWRAP_CMD17, MT6316_TOP_VRCTL_VOSEL_VBUCK1, VOLT_DATA(75000)},
58 {SPM_PWRAP_CMD18, 0, 0},
59 {SPM_PWRAP_CMD19, 0, 0},
60 {SPM_PWRAP_CMD20, 0, 0},
61 {SPM_PWRAP_CMD21, 0, 0},
62 {SPM_PWRAP_CMD22, 0, 0},
63 {SPM_PWRAP_CMD23, 0, 0},
64 {SPM_PWRAP_CMD24, 0, 0},
65 {SPM_PWRAP_CMD25, 0, 0},
66 {SPM_PWRAP_CMD26, 0, 0},
67 {SPM_PWRAP_CMD27, 0, 0},
68 {SPM_PWRAP_CMD28, 0, 0},
69 {SPM_PWRAP_CMD29, 0, 0},
70 {SPM_PWRAP_CMD30, 0, 0},
71 {SPM_PWRAP_CMD31, 0, 0},
72 };
73
74 static struct pmic_wrap_phase_setting phase_table[NR_PMIC_WRAP_PHASE] = {
75 {
76 .cmd = cmd_table,
77 .nr_idx = NR_IDX_ALL,
78 },
79 };
80
81 static struct pmic_wrap_setting pmic_wrap_table = {
82 .phase = phase_table,
83 .phase_nr_idx = NR_PMIC_WRAP_PHASE,
84 };
85
plat_spm_pmic_wrap_init(void)86 void plat_spm_pmic_wrap_init(void)
87 {
88 mt_spm_pmic_wrap_set_table(&pmic_wrap_table);
89 mt_spm_pmic_wrap_set_phase(PMIC_WRAP_PHASE_ALLINONE);
90 }
91