1*ebb44440SRoger Lu /* 2*ebb44440SRoger Lu * Copyright (c) 2020, MediaTek Inc. All rights reserved. 3*ebb44440SRoger Lu * 4*ebb44440SRoger Lu * SPDX-License-Identifier: BSD-3-Clause 5*ebb44440SRoger Lu */ 6*ebb44440SRoger Lu 7*ebb44440SRoger Lu /**************************************************************** 8*ebb44440SRoger Lu * Auto generated by DE, please DO NOT modify this file directly. 9*ebb44440SRoger Lu *****************************************************************/ 10*ebb44440SRoger Lu #ifndef MT_SPM_PMIC_WRAP_H 11*ebb44440SRoger Lu #define MT_SPM_PMIC_WRAP_H 12*ebb44440SRoger Lu 13*ebb44440SRoger Lu enum pmic_wrap_phase_id { 14*ebb44440SRoger Lu PMIC_WRAP_PHASE_ALLINONE, 15*ebb44440SRoger Lu NR_PMIC_WRAP_PHASE, 16*ebb44440SRoger Lu }; 17*ebb44440SRoger Lu 18*ebb44440SRoger Lu /* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */ 19*ebb44440SRoger Lu enum { 20*ebb44440SRoger Lu CMD_0, /* 0x0 */ 21*ebb44440SRoger Lu CMD_1, /* 0x1 */ 22*ebb44440SRoger Lu CMD_2, /* 0x2 */ 23*ebb44440SRoger Lu CMD_3, /* 0x3 */ 24*ebb44440SRoger Lu CMD_4, /* 0x4 */ 25*ebb44440SRoger Lu CMD_5, /* 0x5 */ 26*ebb44440SRoger Lu CMD_6, /* 0x6 */ 27*ebb44440SRoger Lu CMD_7, /* 0x7 */ 28*ebb44440SRoger Lu CMD_8, /* 0x8 */ 29*ebb44440SRoger Lu CMD_9, /* 0x9 */ 30*ebb44440SRoger Lu CMD_10, /* 0xA */ 31*ebb44440SRoger Lu CMD_11, /* 0xB */ 32*ebb44440SRoger Lu CMD_12, /* 0xC */ 33*ebb44440SRoger Lu CMD_13, /* 0xD */ 34*ebb44440SRoger Lu CMD_14, /* 0xE */ 35*ebb44440SRoger Lu CMD_15, /* 0xF */ 36*ebb44440SRoger Lu NR_IDX_ALL, 37*ebb44440SRoger Lu }; 38*ebb44440SRoger Lu 39*ebb44440SRoger Lu /* APIs */ 40*ebb44440SRoger Lu extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); 41*ebb44440SRoger Lu extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, 42*ebb44440SRoger Lu uint32_t idx, uint32_t cmd_wdata); 43*ebb44440SRoger Lu extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, 44*ebb44440SRoger Lu uint32_t idx); 45*ebb44440SRoger Lu #endif /* MT_SPM_PMIC_WRAP_H */ 46