1*7ac6a76cSjason-ch chen /* 2*7ac6a76cSjason-ch chen * Copyright (c) 2022, MediaTek Inc. All rights reserved. 3*7ac6a76cSjason-ch chen * 4*7ac6a76cSjason-ch chen * SPDX-License-Identifier: BSD-3-Clause 5*7ac6a76cSjason-ch chen */ 6*7ac6a76cSjason-ch chen 7*7ac6a76cSjason-ch chen /**************************************************************** 8*7ac6a76cSjason-ch chen * Auto generated by DE, please DO NOT modify this file directly. 9*7ac6a76cSjason-ch chen *****************************************************************/ 10*7ac6a76cSjason-ch chen #ifndef MT_SPM_PMIC_WRAP_H 11*7ac6a76cSjason-ch chen #define MT_SPM_PMIC_WRAP_H 12*7ac6a76cSjason-ch chen 13*7ac6a76cSjason-ch chen enum pmic_wrap_phase_id { 14*7ac6a76cSjason-ch chen PMIC_WRAP_PHASE_ALLINONE = 0U, 15*7ac6a76cSjason-ch chen NR_PMIC_WRAP_PHASE = 1U, 16*7ac6a76cSjason-ch chen }; 17*7ac6a76cSjason-ch chen 18*7ac6a76cSjason-ch chen /* IDX mapping, PMIC_WRAP_PHASE_ALLINONE */ 19*7ac6a76cSjason-ch chen enum { 20*7ac6a76cSjason-ch chen CMD_0 = 0U, /* 0x0 */ 21*7ac6a76cSjason-ch chen CMD_1 = 1U, /* 0x1 */ 22*7ac6a76cSjason-ch chen CMD_2 = 2U, /* 0x2 */ 23*7ac6a76cSjason-ch chen CMD_3 = 3U, /* 0x3 */ 24*7ac6a76cSjason-ch chen CMD_4 = 4U, /* 0x4 */ 25*7ac6a76cSjason-ch chen CMD_5 = 5U, /* 0x5 */ 26*7ac6a76cSjason-ch chen CMD_6 = 6U, /* 0x6 */ 27*7ac6a76cSjason-ch chen CMD_7 = 7U, /* 0x7 */ 28*7ac6a76cSjason-ch chen CMD_8 = 8U, /* 0x8 */ 29*7ac6a76cSjason-ch chen NR_IDX_ALL = 9U, 30*7ac6a76cSjason-ch chen }; 31*7ac6a76cSjason-ch chen 32*7ac6a76cSjason-ch chen /* APIs */ 33*7ac6a76cSjason-ch chen extern void mt_spm_pmic_wrap_set_phase(enum pmic_wrap_phase_id phase); 34*7ac6a76cSjason-ch chen extern void mt_spm_pmic_wrap_set_cmd(enum pmic_wrap_phase_id phase, 35*7ac6a76cSjason-ch chen uint32_t idx, uint32_t cmd_wdata); 36*7ac6a76cSjason-ch chen extern uint64_t mt_spm_pmic_wrap_get_cmd(enum pmic_wrap_phase_id phase, 37*7ac6a76cSjason-ch chen uint32_t idx); 38*7ac6a76cSjason-ch chen 39*7ac6a76cSjason-ch chen #endif /* MT_SPM_PMIC_WRAP_H */ 40