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/rk3399_ARM-atf/lib/debugfs/
H A Ddev.c37 chan_t *channel = NULL; in create_new_channel() local
42 channel = &fdset[i]; in create_new_channel()
43 channel->index = index; in create_new_channel()
48 return channel; in create_new_channel()
68 static int channel_to_fd(chan_t *channel) in channel_to_fd() argument
70 return (channel == NULL) ? -1 : (channel - fdset); in channel_to_fd()
142 static void channel_clear(chan_t *channel) in channel_clear() argument
144 channel->offset = 0; in channel_clear()
145 channel->qid = 0; in channel_clear()
146 channel->index = NODEV; in channel_clear()
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H A Ddevroot.c30 static int rootgen(chan_t *channel, const dirtab_t *tab, int ntab, in rootgen() argument
33 switch (channel->qid & ~CHDIR) { in rootgen()
50 return devgen(channel, tab, ntab, n, dir); in rootgen()
53 static int rootwalk(chan_t *channel, const char *name) in rootwalk() argument
55 return devwalk(channel, name, NULL, 0, rootgen); in rootwalk()
61 static int rootread(chan_t *channel, void *buf, int size) in rootread() argument
66 if ((channel->qid & CHDIR) != 0) { in rootread()
72 return dirread(channel, dir, NULL, 0, rootgen); in rootread()
76 assert(channel->qid != DEV_ROOT_QBLOBCTL); in rootread()
78 dp = &blobtab[channel->qid - DEV_ROOT_QBLOBCTL]; in rootread()
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/rk3399_ARM-atf/drivers/arm/mhu/
H A Dmhu_v3_x.h119 const uint32_t channel, uint32_t flags);
131 const uint32_t channel, uint32_t flags);
144 const uint32_t channel, uint32_t *flags);
157 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
171 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, uint32_t flags);
185 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, uint32_t *flags);
197 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
210 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
223 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
H A Dmhu_v3_x.c134 const uint32_t channel, uint32_t flags) in mhu_v3_x_doorbell_clear() argument
156 mdbcw_reg[channel].mdbcw_clr |= flags; in mhu_v3_x_doorbell_clear()
162 const uint32_t channel, uint32_t flags) in mhu_v3_x_doorbell_write() argument
185 pdbcw_reg[channel].pdbcw_set |= flags; in mhu_v3_x_doorbell_write()
191 const uint32_t channel, uint32_t *flags) in mhu_v3_x_doorbell_read() argument
215 *flags = pdbcw_reg[channel].pdbcw_st; in mhu_v3_x_doorbell_read()
221 *flags = mdbcw_reg[channel].mdbcw_st; in mhu_v3_x_doorbell_read()
231 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, in mhu_v3_x_doorbell_mask_set() argument
255 mdbcw_reg[channel].mdbcw_msk_set |= flags; in mhu_v3_x_doorbell_mask_set()
261 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, in mhu_v3_x_doorbell_mask_clear() argument
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H A Dmhu_v2_x.h96 uint32_t channel, uint32_t val);
113 uint32_t channel, uint32_t *value);
129 uint32_t channel);
146 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value);
163 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
180 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask);
H A Dmhu_v2_x.c209 uint32_t channel, uint32_t val) in mhu_v2_x_channel_send() argument
222 (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_set = val; in mhu_v2_x_channel_send()
230 uint32_t channel, uint32_t *value) in mhu_v2_x_channel_poll() argument
243 *value = (SEND_FRAME(p_mhu))->send_ch_window[channel].ch_st; in mhu_v2_x_channel_poll()
251 uint32_t channel) in mhu_v2_x_channel_clear() argument
264 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_clr = UINT32_MAX; in mhu_v2_x_channel_clear()
272 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value) in mhu_v2_x_channel_receive() argument
285 *value = (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_st; in mhu_v2_x_channel_receive()
293 const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask) in mhu_v2_x_channel_mask_set() argument
306 (RECV_FRAME(p_mhu))->rec_ch_window[channel].ch_msk_set = mask; in mhu_v2_x_channel_mask_set()
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/rk3399_ARM-atf/plat/imx/imx9/common/scmi/
H A Dscmi_client.c22 static scmi_channel_t channel; variable
61 channel.info = &sq_scmi_plat_info; in plat_imx9_scmi_setup()
62 channel.lock = IMX95_SCMI_LOCK_GET_INSTANCE; in plat_imx9_scmi_setup()
63 imx9_scmi_handle = scmi_init(&channel); in plat_imx9_scmi_setup()
68 if (scmi_ap_core_init(&channel) < 0) { in plat_imx9_scmi_setup()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c125 static __pmusramfunc void rkclk_ddr_reset(uint32_t channel, uint32_t ctl, in rkclk_ddr_reset() argument
128 channel &= 0x1; in rkclk_ddr_reset()
132 CRU_SFTRST_DDR_CTRL(channel, ctl) | in rkclk_ddr_reset()
133 CRU_SFTRST_DDR_PHY(channel, phy)); in rkclk_ddr_reset()
431 unsigned char channel, uint32_t ddrconfig) in set_ddrconfig() argument
434 struct rk3399_sdram_channel *ch = &sdram_params->ch[channel]; in set_ddrconfig()
446 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICECONF, in set_ddrconfig()
448 mmio_write_32(MSCH_BASE(channel) + MSCH_DEVICESIZE, in set_ddrconfig()
787 uint32_t channel; in dmc_resume() local
811 for (channel = 0; channel < sdram_params->num_channels; channel++) { in dmc_resume()
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H A Ddfs.c82 uint8_t channel, uint8_t cs) in get_cs_die_capability() argument
84 struct rk3399_sdram_channel *ch = &ram_config->ch[channel]; in get_cs_die_capability()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_boardid.c63 static int get_adc(unsigned int channel, unsigned int *value) in get_adc() argument
67 if (channel > HKADC_CHANNEL_MAX) { in get_adc()
68 WARN("invalid channel:%d\n", channel); in get_adc()
72 mmio_write_32(HKADC_WR01_DATA_REG, HKADC_WR01_VALUE | channel); in get_adc()
97 static int get_value(unsigned int channel, unsigned int *value) in get_value() argument
101 ret = get_adc(channel, value); in get_value()
/rk3399_ARM-atf/plat/socionext/synquacer/drivers/scp/
H A Dsq_scmi.c94 static scmi_channel_t channel; variable
226 channel.info = &sq_scmi_plat_info; in plat_sq_pwrc_setup()
227 channel.lock = SQ_SCMI_LOCK_GET_INSTANCE; in plat_sq_pwrc_setup()
228 sq_scmi_handle = scmi_init(&channel); in plat_sq_pwrc_setup()
233 if (scmi_ap_core_init(&channel) < 0) { in plat_sq_pwrc_setup()
/rk3399_ARM-atf/drivers/marvell/secure_dfx_access/
H A Darmada_thermal.c166 static void armada_select_channel(int channel) in armada_select_channel() argument
179 if (channel) { in armada_select_channel()
185 ctrl0 |= (channel - 1) << TSEN_CTRL0_CHAN_SHIFT; in armada_select_channel()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c983 uint8_t channel = cfg->id; in clk_flexgen_recalc() local
986 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) & in clk_flexgen_recalc()
988 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & in clk_flexgen_recalc()
1034 uint8_t channel = cfg->id; in clk_flexgen_gate_enable() local
1036 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), in clk_flexgen_gate_enable()
1047 uint8_t channel = cfg->id; in clk_flexgen_gate_disable() local
1049 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), in clk_flexgen_gate_disable()
1058 uint8_t channel = cfg->id; in clk_flexgen_gate_is_enabled() local
1060 return !!(mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & in clk_flexgen_gate_is_enabled()
1864 static int wait_predivsr(uint16_t channel) in wait_predivsr() argument
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/rk3399_ARM-atf/docs/threat_model/firmware_threat_model/
H A Dthreat_model_rse_interface.rst36 | | channel to record boot measurements and get image |
H A Dthreat_model.rst169 analysis side-channel attacks represent a category of security threats that
317 | | side-channel information that can be used by an |
634 | | | A timing side-channel attack is a type of attack |
1072 | | | Microarchitectural side-channel attacks such as |
1097 | Mitigations | Enable appropriate side-channel protections. |
1116 | | mount side-channel attacks using information |
1124 | | side-channel timing attacks against TF-A. |
/rk3399_ARM-atf/docs/design_documents/
H A Drse.rst51 exchanged over the MHU channels. A channel is capable of delivering a single
52 word. The sender writes the data to the channel register on its side and the
53 receiver can read the data from the channel on the other side. One dedicated
54 channel is used for signalling. It does not deliver any payload it is just
55 meant for signalling that the sender loaded the data to the channel registers
56 so the receiver can read them. The receiver uses the same channel to signal
58 the data fit to the channel registers then the message is sent over in
60 messages. Data is copied from/to these buffers to/from the channel registers.
H A Dpsci_osi_mode.rst78 would have to communicate with an API side channel to know when it can do so.
84 eliminates the need for a side channel, and uses the well documented API between
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst352 communication channel. This is compounded by the SCP firmware waiting for each
353 AP CPU to enter WFI before making the channel available to other CPUs, which
/rk3399_ARM-atf/docs/about/
H A Dlts.rst241 #. Maintainers collaborate in the following discord channel -
244 mentioned discord channel.
287 positive. If in doubt, that can be discussed either in the “tf-a-lts” channel
366 d. gentle ping in LTS discord channel asking for reviews to ensure
/rk3399_ARM-atf/fdts/
H A Dstm32mp25-lpddr4-1x16Gbits-1x32bits-1200MHz.dtsi14 * density 8Gbits (per 16bit channel)
H A Dstm32mp25-lpddr4-1x32Gbits-1x32bits-1200MHz.dtsi14 * density 16Gbits (per 16bit channel)
H A Dstm32mp25-lpddr4-2x16Gbits-32bits-1200MHz.dtsi14 * density 16Gbits (per 16bit channel)
/rk3399_ARM-atf/docs/process/
H A Dsecurity-hardening.rst72 would allow it to carry out side-channel timing attacks against the Secure
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-10.rst79 retrieved through some side-channel attacks as part of a more complex attack.
/rk3399_ARM-atf/plat/intel/soc/common/
H A Dsocfpga_sip_svc.c1351 uint32_t channel = (uint32_t)x2; local
1358 &channel,

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