1*af26d7d6STamas Ban /* 2*af26d7d6STamas Ban * Copyright (c) 2020-2022, Arm Limited. All rights reserved. 3*af26d7d6STamas Ban * 4*af26d7d6STamas Ban * SPDX-License-Identifier: BSD-3-Clause 5*af26d7d6STamas Ban */ 6*af26d7d6STamas Ban 7*af26d7d6STamas Ban #ifndef MHU_V2_X_H 8*af26d7d6STamas Ban #define MHU_V2_X_H 9*af26d7d6STamas Ban 10*af26d7d6STamas Ban #include <stdbool.h> 11*af26d7d6STamas Ban #include <stdint.h> 12*af26d7d6STamas Ban 13*af26d7d6STamas Ban #define MHU_2_X_INTR_NR2R_OFF (0x0u) 14*af26d7d6STamas Ban #define MHU_2_X_INTR_R2NR_OFF (0x1u) 15*af26d7d6STamas Ban #define MHU_2_1_INTR_CHCOMB_OFF (0x2u) 16*af26d7d6STamas Ban 17*af26d7d6STamas Ban #define MHU_2_X_INTR_NR2R_MASK (0x1u << MHU_2_X_INTR_NR2R_OFF) 18*af26d7d6STamas Ban #define MHU_2_X_INTR_R2NR_MASK (0x1u << MHU_2_X_INTR_R2NR_OFF) 19*af26d7d6STamas Ban #define MHU_2_1_INTR_CHCOMB_MASK (0x1u << MHU_2_1_INTR_CHCOMB_OFF) 20*af26d7d6STamas Ban 21*af26d7d6STamas Ban enum mhu_v2_x_frame_t { 22*af26d7d6STamas Ban MHU_V2_X_SENDER_FRAME = 0x0u, 23*af26d7d6STamas Ban MHU_V2_X_RECEIVER_FRAME = 0x1u, 24*af26d7d6STamas Ban }; 25*af26d7d6STamas Ban 26*af26d7d6STamas Ban enum mhu_v2_x_supported_revisions { 27*af26d7d6STamas Ban MHU_REV_READ_FROM_HW = 0, 28*af26d7d6STamas Ban MHU_REV_2_0, 29*af26d7d6STamas Ban MHU_REV_2_1, 30*af26d7d6STamas Ban }; 31*af26d7d6STamas Ban 32*af26d7d6STamas Ban struct mhu_v2_x_dev_t { 33*af26d7d6STamas Ban uintptr_t base; 34*af26d7d6STamas Ban enum mhu_v2_x_frame_t frame; 35*af26d7d6STamas Ban uint32_t subversion; /*!< Hardware subversion: v2.X */ 36*af26d7d6STamas Ban bool is_initialized; /*!< Indicates if the MHU driver 37*af26d7d6STamas Ban * is initialized and enabled 38*af26d7d6STamas Ban */ 39*af26d7d6STamas Ban }; 40*af26d7d6STamas Ban 41*af26d7d6STamas Ban /** 42*af26d7d6STamas Ban * MHU v2 error enumeration types. 43*af26d7d6STamas Ban */ 44*af26d7d6STamas Ban enum mhu_v2_x_error_t { 45*af26d7d6STamas Ban MHU_V_2_X_ERR_NONE = 0, 46*af26d7d6STamas Ban MHU_V_2_X_ERR_NOT_INIT = -1, 47*af26d7d6STamas Ban MHU_V_2_X_ERR_ALREADY_INIT = -2, 48*af26d7d6STamas Ban MHU_V_2_X_ERR_UNSUPPORTED_VERSION = -3, 49*af26d7d6STamas Ban MHU_V_2_X_ERR_INVALID_ARG = -4, 50*af26d7d6STamas Ban MHU_V_2_X_ERR_GENERAL = -5 51*af26d7d6STamas Ban }; 52*af26d7d6STamas Ban 53*af26d7d6STamas Ban /** 54*af26d7d6STamas Ban * Initializes the driver. 55*af26d7d6STamas Ban * 56*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 57*af26d7d6STamas Ban * rev MHU revision (if can't be identified from HW). 58*af26d7d6STamas Ban * 59*af26d7d6STamas Ban * Reads the MHU hardware version. 60*af26d7d6STamas Ban * 61*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 62*af26d7d6STamas Ban * 63*af26d7d6STamas Ban * MHU revision only has to be specified when versions can't be read 64*af26d7d6STamas Ban * from HW (ARCH_MAJOR_REV reg reads as 0x0). 65*af26d7d6STamas Ban * 66*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 67*af26d7d6STamas Ban */ 68*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_driver_init(struct mhu_v2_x_dev_t *dev, 69*af26d7d6STamas Ban enum mhu_v2_x_supported_revisions rev); 70*af26d7d6STamas Ban 71*af26d7d6STamas Ban /** 72*af26d7d6STamas Ban * Returns the number of channels implemented. 73*af26d7d6STamas Ban * 74*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 75*af26d7d6STamas Ban * 76*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 77*af26d7d6STamas Ban */ 78*af26d7d6STamas Ban uint32_t mhu_v2_x_get_num_channel_implemented( 79*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev); 80*af26d7d6STamas Ban 81*af26d7d6STamas Ban /** 82*af26d7d6STamas Ban * Sends the value over a channel. 83*af26d7d6STamas Ban * 84*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 85*af26d7d6STamas Ban * channel Channel to send the value over. 86*af26d7d6STamas Ban * val Value to send. 87*af26d7d6STamas Ban * 88*af26d7d6STamas Ban * Sends the value over a channel. 89*af26d7d6STamas Ban * 90*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 91*af26d7d6STamas Ban * 92*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 93*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 94*af26d7d6STamas Ban */ 95*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_send(const struct mhu_v2_x_dev_t *dev, 96*af26d7d6STamas Ban uint32_t channel, uint32_t val); 97*af26d7d6STamas Ban 98*af26d7d6STamas Ban /** 99*af26d7d6STamas Ban * Polls sender channel status. 100*af26d7d6STamas Ban * 101*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 102*af26d7d6STamas Ban * channel Channel to poll the status of. 103*af26d7d6STamas Ban * value Pointer to variable that will store the value. 104*af26d7d6STamas Ban * 105*af26d7d6STamas Ban * Polls sender channel status. 106*af26d7d6STamas Ban * 107*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 108*af26d7d6STamas Ban * 109*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 110*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 111*af26d7d6STamas Ban */ 112*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_poll(const struct mhu_v2_x_dev_t *dev, 113*af26d7d6STamas Ban uint32_t channel, uint32_t *value); 114*af26d7d6STamas Ban 115*af26d7d6STamas Ban /** 116*af26d7d6STamas Ban * Clears the channel after the value is send over it. 117*af26d7d6STamas Ban * 118*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 119*af26d7d6STamas Ban * channel Channel to clear. 120*af26d7d6STamas Ban * 121*af26d7d6STamas Ban * Clears the channel after the value is send over it. 122*af26d7d6STamas Ban * 123*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code.. 124*af26d7d6STamas Ban * 125*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 126*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 127*af26d7d6STamas Ban */ 128*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_clear(const struct mhu_v2_x_dev_t *dev, 129*af26d7d6STamas Ban uint32_t channel); 130*af26d7d6STamas Ban 131*af26d7d6STamas Ban /** 132*af26d7d6STamas Ban * Receives the value over a channel. 133*af26d7d6STamas Ban * 134*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 135*af26d7d6STamas Ban * channel Channel to receive the value from. 136*af26d7d6STamas Ban * value Pointer to variable that will store the value. 137*af26d7d6STamas Ban * 138*af26d7d6STamas Ban * Receives the value over a channel. 139*af26d7d6STamas Ban * 140*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 141*af26d7d6STamas Ban * 142*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 143*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 144*af26d7d6STamas Ban */ 145*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_receive( 146*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t *value); 147*af26d7d6STamas Ban 148*af26d7d6STamas Ban /** 149*af26d7d6STamas Ban * Sets bits in the Channel Mask. 150*af26d7d6STamas Ban * 151*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 152*af26d7d6STamas Ban * channel Which channel's mask to set. 153*af26d7d6STamas Ban * mask Mask to be set over a receiver frame. 154*af26d7d6STamas Ban * 155*af26d7d6STamas Ban * Sets bits in the Channel Mask. 156*af26d7d6STamas Ban * 157*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code.. 158*af26d7d6STamas Ban * 159*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 160*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 161*af26d7d6STamas Ban */ 162*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_mask_set( 163*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); 164*af26d7d6STamas Ban 165*af26d7d6STamas Ban /** 166*af26d7d6STamas Ban * Clears bits in the Channel Mask. 167*af26d7d6STamas Ban * 168*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 169*af26d7d6STamas Ban * channel Which channel's mask to clear. 170*af26d7d6STamas Ban * mask Mask to be clear over a receiver frame. 171*af26d7d6STamas Ban * 172*af26d7d6STamas Ban * Clears bits in the Channel Mask. 173*af26d7d6STamas Ban * 174*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 175*af26d7d6STamas Ban * 176*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 177*af26d7d6STamas Ban * This function doesn't check if channel is implemented. 178*af26d7d6STamas Ban */ 179*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_channel_mask_clear( 180*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev, uint32_t channel, uint32_t mask); 181*af26d7d6STamas Ban 182*af26d7d6STamas Ban /** 183*af26d7d6STamas Ban * Initiates a MHU transfer with the handshake signals. 184*af26d7d6STamas Ban * 185*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 186*af26d7d6STamas Ban * 187*af26d7d6STamas Ban * Initiates a MHU transfer with the handshake signals in a blocking mode. 188*af26d7d6STamas Ban * 189*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 190*af26d7d6STamas Ban * 191*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 192*af26d7d6STamas Ban */ 193*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_initiate_transfer( 194*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev); 195*af26d7d6STamas Ban 196*af26d7d6STamas Ban /** 197*af26d7d6STamas Ban * Closes a MHU transfer with the handshake signals. 198*af26d7d6STamas Ban * 199*af26d7d6STamas Ban * dev MHU device struct mhu_v2_x_dev_t. 200*af26d7d6STamas Ban * 201*af26d7d6STamas Ban * Closes a MHU transfer with the handshake signals in a blocking mode. 202*af26d7d6STamas Ban * 203*af26d7d6STamas Ban * Returns mhu_v2_x_error_t error code. 204*af26d7d6STamas Ban * 205*af26d7d6STamas Ban * This function doesn't check if dev is NULL. 206*af26d7d6STamas Ban */ 207*af26d7d6STamas Ban enum mhu_v2_x_error_t mhu_v2_x_close_transfer( 208*af26d7d6STamas Ban const struct mhu_v2_x_dev_t *dev); 209*af26d7d6STamas Ban 210*af26d7d6STamas Ban #endif /* MHU_V2_X_H */ 211