xref: /rk3399_ARM-atf/drivers/arm/mhu/mhu_v3_x.h (revision 25a0695888878ad7258823e283f76bab69a95f23)
1*bc174764SAziz IDOMAR /*
2*bc174764SAziz IDOMAR  * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
3*bc174764SAziz IDOMAR  *
4*bc174764SAziz IDOMAR  * SPDX-License-Identifier: BSD-3-Clause
5*bc174764SAziz IDOMAR  */
6*bc174764SAziz IDOMAR 
7*bc174764SAziz IDOMAR #ifndef MHU_V3_X_H
8*bc174764SAziz IDOMAR #define MHU_V3_X_H
9*bc174764SAziz IDOMAR 
10*bc174764SAziz IDOMAR #include <stdbool.h>
11*bc174764SAziz IDOMAR #include <stdint.h>
12*bc174764SAziz IDOMAR 
13*bc174764SAziz IDOMAR /* MHU Architecture Major Revision 3 */
14*bc174764SAziz IDOMAR #define MHU_MAJOR_REV_V3 U(0x2)
15*bc174764SAziz IDOMAR /* MHU Architecture Minor Revision 0 */
16*bc174764SAziz IDOMAR #define MHU_MINOR_REV_3_0 U(0x0)
17*bc174764SAziz IDOMAR 
18*bc174764SAziz IDOMAR /* MHU Architecture Major Revision offset */
19*bc174764SAziz IDOMAR #define MHU_ARCH_MAJOR_REV_OFF U(0x4)
20*bc174764SAziz IDOMAR /* MHU Architecture Major Revision mask */
21*bc174764SAziz IDOMAR #define MHU_ARCH_MAJOR_REV_MASK (U(0xf) << MHU_ARCH_MAJOR_REV_OFF)
22*bc174764SAziz IDOMAR 
23*bc174764SAziz IDOMAR /* MHU Architecture Minor Revision offset */
24*bc174764SAziz IDOMAR #define MHU_ARCH_MINOR_REV_OFF U(0x0)
25*bc174764SAziz IDOMAR /* MHU Architecture Minor Revision mask */
26*bc174764SAziz IDOMAR #define MHU_ARCH_MINOR_REV_MASK (U(0xf) << MHU_ARCH_MINOR_REV_OFF)
27*bc174764SAziz IDOMAR 
28*bc174764SAziz IDOMAR /* MHUv3 PBX/MBX Operational Request offset */
29*bc174764SAziz IDOMAR #define MHU_V3_OP_REQ_OFF U(0)
30*bc174764SAziz IDOMAR /* MHUv3 PBX/MBX Operational Request */
31*bc174764SAziz IDOMAR #define MHU_V3_OP_REQ (U(1) << MHU_V3_OP_REQ_OFF)
32*bc174764SAziz IDOMAR 
33*bc174764SAziz IDOMAR /**
34*bc174764SAziz IDOMAR  * MHUv3 error enumeration types
35*bc174764SAziz IDOMAR  */
36*bc174764SAziz IDOMAR enum mhu_v3_x_error_t {
37*bc174764SAziz IDOMAR 	/* No error */
38*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_NONE,
39*bc174764SAziz IDOMAR 	/* MHU driver not initialized */
40*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_NOT_INIT,
41*bc174764SAziz IDOMAR 	/* MHU driver alreary initialized */
42*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_ALREADY_INIT,
43*bc174764SAziz IDOMAR 	/* MHU Revision not supported error */
44*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_UNSUPPORTED_VERSION,
45*bc174764SAziz IDOMAR 	/* Operation not supported */
46*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_UNSUPPORTED,
47*bc174764SAziz IDOMAR 	/* Invalid parameter */
48*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_INVALID_PARAM,
49*bc174764SAziz IDOMAR 	/* General MHU driver error */
50*bc174764SAziz IDOMAR 	MHU_V_3_X_ERR_GENERAL,
51*bc174764SAziz IDOMAR };
52*bc174764SAziz IDOMAR 
53*bc174764SAziz IDOMAR /**
54*bc174764SAziz IDOMAR  * MHUv3 channel types
55*bc174764SAziz IDOMAR  */
56*bc174764SAziz IDOMAR enum mhu_v3_x_channel_type_t {
57*bc174764SAziz IDOMAR 	/* Doorbell channel */
58*bc174764SAziz IDOMAR 	MHU_V3_X_CHANNEL_TYPE_DBCH,
59*bc174764SAziz IDOMAR 	/* Channel type count */
60*bc174764SAziz IDOMAR 	MHU_V3_X_CHANNEL_TYPE_COUNT,
61*bc174764SAziz IDOMAR };
62*bc174764SAziz IDOMAR 
63*bc174764SAziz IDOMAR /**
64*bc174764SAziz IDOMAR  * MHUv3 frame types
65*bc174764SAziz IDOMAR  */
66*bc174764SAziz IDOMAR enum mhu_v3_x_frame_t {
67*bc174764SAziz IDOMAR 	/* MHUv3 postbox frame */
68*bc174764SAziz IDOMAR 	MHU_V3_X_PBX_FRAME,
69*bc174764SAziz IDOMAR 	/* MHUv3 mailbox frame */
70*bc174764SAziz IDOMAR 	MHU_V3_X_MBX_FRAME,
71*bc174764SAziz IDOMAR };
72*bc174764SAziz IDOMAR 
73*bc174764SAziz IDOMAR /**
74*bc174764SAziz IDOMAR  * MHUv3 device structure
75*bc174764SAziz IDOMAR  */
76*bc174764SAziz IDOMAR struct mhu_v3_x_dev_t {
77*bc174764SAziz IDOMAR 	/* Base address of the MHUv3 frame */
78*bc174764SAziz IDOMAR 	uintptr_t base;
79*bc174764SAziz IDOMAR 	/* Type of the MHUv3 frame */
80*bc174764SAziz IDOMAR 	enum mhu_v3_x_frame_t frame;
81*bc174764SAziz IDOMAR 	/* Minor revision of the MHUv3 */
82*bc174764SAziz IDOMAR 	uint32_t subversion;
83*bc174764SAziz IDOMAR 	/* Flag to indicate if the MHUv3 is initialized */
84*bc174764SAziz IDOMAR 	bool is_initialized;
85*bc174764SAziz IDOMAR };
86*bc174764SAziz IDOMAR 
87*bc174764SAziz IDOMAR /**
88*bc174764SAziz IDOMAR  * Initializes the MHUv3
89*bc174764SAziz IDOMAR  *
90*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
91*bc174764SAziz IDOMAR  *
92*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
93*bc174764SAziz IDOMAR  */
94*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_driver_init(struct mhu_v3_x_dev_t *dev);
95*bc174764SAziz IDOMAR 
96*bc174764SAziz IDOMAR /**
97*bc174764SAziz IDOMAR  * Returns the number of channels implemented
98*bc174764SAziz IDOMAR  *
99*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
100*bc174764SAziz IDOMAR  * ch_type	MHU channel type mhu_v3_x_channel_type_t
101*bc174764SAziz IDOMAR  * num_ch	Pointer to the variable that will store the value
102*bc174764SAziz IDOMAR  *
103*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
104*bc174764SAziz IDOMAR  */
105*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_get_num_channel_implemented(
106*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, enum mhu_v3_x_channel_type_t ch_type,
107*bc174764SAziz IDOMAR 	 uint8_t *num_ch);
108*bc174764SAziz IDOMAR 
109*bc174764SAziz IDOMAR /**
110*bc174764SAziz IDOMAR  * Clear flags from a doorbell channel
111*bc174764SAziz IDOMAR  *
112*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
113*bc174764SAziz IDOMAR  * channel	Doorbell channel number
114*bc174764SAziz IDOMAR  * flags	Flags to be cleared from the channel
115*bc174764SAziz IDOMAR  *
116*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
117*bc174764SAziz IDOMAR  */
118*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_clear(const struct mhu_v3_x_dev_t *dev,
119*bc174764SAziz IDOMAR 	 const uint32_t channel, uint32_t flags);
120*bc174764SAziz IDOMAR 
121*bc174764SAziz IDOMAR /**
122*bc174764SAziz IDOMAR  * Write flags to a doorbell channel
123*bc174764SAziz IDOMAR  *
124*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
125*bc174764SAziz IDOMAR  * channel	Doorbell channel number
126*bc174764SAziz IDOMAR  * flags	Flags to be written to the channel
127*bc174764SAziz IDOMAR  *
128*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
129*bc174764SAziz IDOMAR  */
130*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_write(const struct mhu_v3_x_dev_t *dev,
131*bc174764SAziz IDOMAR 	 const uint32_t channel, uint32_t flags);
132*bc174764SAziz IDOMAR 
133*bc174764SAziz IDOMAR /**
134*bc174764SAziz IDOMAR  * Read value from a doorbell channel
135*bc174764SAziz IDOMAR  *
136*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
137*bc174764SAziz IDOMAR  * channel	Doorbell channel number
138*bc174764SAziz IDOMAR  * flags	Pointer to the variable that will store the flags read from the
139*bc174764SAziz IDOMAR  *		channel
140*bc174764SAziz IDOMAR  *
141*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
142*bc174764SAziz IDOMAR  */
143*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_read(const struct mhu_v3_x_dev_t *dev,
144*bc174764SAziz IDOMAR 	 const uint32_t channel, uint32_t *flags);
145*bc174764SAziz IDOMAR 
146*bc174764SAziz IDOMAR /**
147*bc174764SAziz IDOMAR  * Set bits in a doorbell channel mask which is used to disable interrupts for
148*bc174764SAziz IDOMAR  * received flags corresponding to the mask
149*bc174764SAziz IDOMAR  *
150*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
151*bc174764SAziz IDOMAR  * channel	Doorbell channel number
152*bc174764SAziz IDOMAR  * flags	Flags to set mask bits in this doorbell channel
153*bc174764SAziz IDOMAR  *
154*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
155*bc174764SAziz IDOMAR  */
156*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_mask_set(
157*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
158*bc174764SAziz IDOMAR 	 uint32_t flags);
159*bc174764SAziz IDOMAR 
160*bc174764SAziz IDOMAR /**
161*bc174764SAziz IDOMAR  * Clear bits in a doorbell channel mask which is used to disable interrupts
162*bc174764SAziz IDOMAR  * for received flags corresponding to the mask
163*bc174764SAziz IDOMAR  *
164*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
165*bc174764SAziz IDOMAR  * channel	Doorbell channel number
166*bc174764SAziz IDOMAR  * flags	Flags to clear mask bits in this doorbell channel
167*bc174764SAziz IDOMAR  *
168*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
169*bc174764SAziz IDOMAR  */
170*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_mask_clear(
171*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, uint32_t flags);
172*bc174764SAziz IDOMAR 
173*bc174764SAziz IDOMAR /**
174*bc174764SAziz IDOMAR  * Get the mask of a doorbell channel which is used to disable interrupts for
175*bc174764SAziz IDOMAR  * received flags corresponding to the mask
176*bc174764SAziz IDOMAR  *
177*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
178*bc174764SAziz IDOMAR  * channel	Doorbell channel number
179*bc174764SAziz IDOMAR  * flags	Pointer to the variable that will store the flags read from the
180*bc174764SAziz IDOMAR  *		mask value
181*bc174764SAziz IDOMAR  *
182*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
183*bc174764SAziz IDOMAR  */
184*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_doorbell_mask_get(
185*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel, uint32_t *flags);
186*bc174764SAziz IDOMAR 
187*bc174764SAziz IDOMAR /**
188*bc174764SAziz IDOMAR  * Enable the channel interrupt
189*bc174764SAziz IDOMAR  *
190*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
191*bc174764SAziz IDOMAR  * channel	Doorbell channel number
192*bc174764SAziz IDOMAR  * ch_type	MHU channel type mhu_v3_x_channel_type_t
193*bc174764SAziz IDOMAR  *
194*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
195*bc174764SAziz IDOMAR  */
196*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_channel_interrupt_enable(
197*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
198*bc174764SAziz IDOMAR 	 enum mhu_v3_x_channel_type_t ch_type);
199*bc174764SAziz IDOMAR 
200*bc174764SAziz IDOMAR /**
201*bc174764SAziz IDOMAR  * Disable the channel interrupt
202*bc174764SAziz IDOMAR  *
203*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
204*bc174764SAziz IDOMAR  * channel	Doorbell channel number
205*bc174764SAziz IDOMAR  * ch_type	MHU channel type mhu_v3_x_channel_type_t
206*bc174764SAziz IDOMAR  *
207*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
208*bc174764SAziz IDOMAR  */
209*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_channel_interrupt_disable(
210*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
211*bc174764SAziz IDOMAR 	 enum mhu_v3_x_channel_type_t ch_type);
212*bc174764SAziz IDOMAR 
213*bc174764SAziz IDOMAR /**
214*bc174764SAziz IDOMAR  * Clear the channel interrupt
215*bc174764SAziz IDOMAR  *
216*bc174764SAziz IDOMAR  * dev		MHU device struct mhu_v3_x_dev_t
217*bc174764SAziz IDOMAR  * channel	Doorbell channel number
218*bc174764SAziz IDOMAR  * ch_type	MHU channel type mhu_v3_x_channel_type_t
219*bc174764SAziz IDOMAR  *
220*bc174764SAziz IDOMAR  * Returns mhu_v3_x_error_t error code
221*bc174764SAziz IDOMAR  */
222*bc174764SAziz IDOMAR enum mhu_v3_x_error_t mhu_v3_x_channel_interrupt_clear(
223*bc174764SAziz IDOMAR 	 const struct mhu_v3_x_dev_t *dev, const uint32_t channel,
224*bc174764SAziz IDOMAR 	 enum mhu_v3_x_channel_type_t ch_type);
225*bc174764SAziz IDOMAR 
226*bc174764SAziz IDOMAR #endif /* MHU_V3_X_H */
227