| /rk3399_ARM-atf/plat/amd/versal2/include/ |
| H A D | def.h | 161 #define UART0_BASE U(0xF1920000) macro
167 #define UART_BASE UART0_BASE
184 # define RT_UART_BASE UART0_BASE
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| /rk3399_ARM-atf/plat/rockchip/rk3576/ |
| H A D | rk3576_def.h | 116 #define UART0_BASE 0x2ad40000 macro
193 #define RK_DBG_UART_BASE UART0_BASE
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| /rk3399_ARM-atf/plat/rockchip/rk3368/ |
| H A D | rk3368_def.h | 38 #define UART0_BASE 0xff180000 macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/ |
| H A D | bl31_plat_setup.c | 75 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/mediatek/mt8195/ |
| H A D | bl31_plat_setup.c | 75 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/ |
| H A D | bl31_plat_setup.c | 76 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/rockchip/rk3568/ |
| H A D | rk3568_def.h | 46 #define UART0_BASE 0xfdd50000 macro
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| /rk3399_ARM-atf/plat/rockchip/rk3288/ |
| H A D | rk3288_def.h | 31 #define UART0_BASE 0xff180000 macro
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| /rk3399_ARM-atf/plat/qemu/qemu/include/ |
| H A D | platform_def.h | 211 #define UART0_BASE 0x09000000 macro
216 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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| /rk3399_ARM-atf/plat/mediatek/mt8192/include/ |
| H A D | platform_def.h | 66 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3328/ |
| H A D | rk3328_def.h | 18 #define UART0_BASE 0xff110000 macro
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| /rk3399_ARM-atf/plat/mediatek/mt8186/include/ |
| H A D | platform_def.h | 59 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8195/include/ |
| H A D | platform_def.h | 70 #define UART0_BASE (IO_PHYS + 0x01001100) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8183/ |
| H A D | bl31_plat_setup.c | 127 console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console); in bl31_early_platform_setup2()
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| /rk3399_ARM-atf/plat/rockchip/px30/ |
| H A D | px30_def.h | 31 #define UART0_BASE 0xff030000 macro
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| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/ |
| H A D | platform_def.h | 229 #define UART0_BASE 0x60000000 macro
238 #define PLAT_QEMU_BOOT_UART_BASE UART0_BASE
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| /rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/ |
| H A D | addressmap_shared.h | 21 #define UART0_BASE (MMIO_BASE + 0x07180000) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/ |
| H A D | rk3588_def.h | 82 #define UART0_BASE 0xfd890000 macro
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| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | params_setup.c | 83 uart_base = UART0_BASE; in plat_rockchip_dt_process_fdt_uart()
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| /rk3399_ARM-atf/plat/mediatek/mt8189/include/ |
| H A D | platform_def.h | 75 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /rk3399_ARM-atf/plat/mediatek/mt8188/include/ |
| H A D | platform_def.h | 77 #define UART0_BASE (IO_PHYS + 0x01002000) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.c | 22 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
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| /rk3399_ARM-atf/plat/mediatek/mt8196/include/ |
| H A D | platform_def.h | 111 #define UART0_BASE (IO_PHYS + 0x06000000) macro
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| /rk3399_ARM-atf/plat/mediatek/drivers/uart/ |
| H A D | uart.c | 13 UART0_BASE,
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| /rk3399_ARM-atf/plat/mediatek/mt8183/include/ |
| H A D | platform_def.h | 99 #define UART0_BASE (IO_PHYS + 0x01002000) macro
|