Searched refs:TZC (Results 1 – 20 of 20) sorted by relevance
44 mem_size = <0x200000>; /* 2MB TZC DRAM */51 mem_size = <0x200000>; /* 2MB TZC DRAM */58 mem_size = <0xe00000>; /* 14MB TZC DRAM */
15 mem_size = <0xb00000>; /* 11MB TZC DRAM */
15 mem_size = <0x3f00000>; /* 64MB TZC DRAM - 1MB align */
22 $(info -> No TZC present on platform)24 $(error -> TZC type not set!)
31 # TZC IP Details TZC used is TZC380 or TZC400
26 # TZC IP Details TZC used is TZC380 or TZC400
77 .. |TZC| replace:: :term:`TZC`
273 TZC
117 …- add extra DRAM configuration for TZC ([887cdf4](https://review.trustedfirmware.org/plugins/gitil…1995 …- exclude extend memory map TZC regions ([06cec93](https://review.trustedfirmware.org/plugins/giti…2636 …- don't enable TZC on TC3 ([8ce29a7](https://review.trustedfirmware.org/plugins/gitiles/TF-A/trust…3075 …- allow SIMD context to be put in TZC DRAM ([b4c23ad](https://review.trustedfirmware.org/plugins/g…6185 …- copy the Event Log to TZC secured DRAM area ([191aa5d](https://review.trustedfirmware.org/plugin…7963 - **TZC**7965 - **TZC-380**8020 - **TZC-380**8481 - **TZC**8483 - **TZC-400**[all …]
617 - Configure the platforms TrustZone Controller (TZC) with appropriate regions2081 example, Arm standard platforms initialize the TZC controller so that the
27 # TZC IP Details TZC used is TZC380 or TZC400
35 clk_enable(TZC); in stm32mp1_arch_security_setup()
77 #define TZC 49 macro
26 # TZC used is TZC380 or TZC400
7 - ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also
23 Controller (TZC).
74 configure the TrustZone Controller (TZC) to create a region in the DRAM1865 Loading the BL32 image in TZC secured DRAM doesn't change the memory1890 | EL3 TZC |1892 | AP TZC |1935 | EL3 TZC |1937 | AP TZC |1973 **FVP with TSP in TZC-Secured DRAM with firmware configs :**1979 | EL3 TZC |1981 | AP TZC |2024 | SCP TZC |[all …]
99 On FVP platform datastore is allocated from TZC DRAM section.
1934 STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC),