Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 ma

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 map for mboot
feat(rpi3): add dTPM backed measured boot
feat(tpm): add Infineon SLB9670 GPIO SPI config
feat(tpm): add tpm drivers and framework
feat(io): add generic gpio spi bit-bang driver
feat(rpi3): implement eventlog handoff to BL33
feat(rpi3): implement mboot for rpi3

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docs(tpm): add design documentation for dTPM

-documentation for Discrete TPM drivers.
-documentation for a proof of concept on rpi3;
Measured Boot using Discrete TPM.

Signed-off-by: Abhi Singh <ab

docs(tpm): add design documentation for dTPM

-documentation for Discrete TPM drivers.
-documentation for a proof of concept on rpi3;
Measured Boot using Discrete TPM.

Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Change-Id: If8e7c14a1c0b9776af872104aceeff21a13bd821

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Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): add DPE to RSE desing doc
feat(docs): add RSE provided mboot backends to the threat model
feat(docs): update mboot t

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): add DPE to RSE desing doc
feat(docs): add RSE provided mboot backends to the threat model
feat(docs): update mboot threat model

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feat(docs): add DPE to RSE desing doc

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: Iec38be8a3eb93a54d9b5bc7db7a7ff8c126920ac

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I23

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I234a2400d00fea606c5312ebddf94e2624463ff8

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feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the poss

feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the possible attacks.
- Rephrase the section that describes the Measured Boot backends.

Change-Id: I6577a56184992bf16f4aa1b773d1636781cbb049
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Chan

docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge "docs(threat-model): add a notes related to the Measured Boot" into integration

docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measur

docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measurements are just stored into a TCG-compatible event
log buffer in secure memory.

In light of the fact that Event Log measurements are taken by BL1 and
BL2, we need to trust these components to store genuine measurements,
and the Generic Threat Model always mitigates against attacks on these
components, therefore, there is no explicit document for the Measured
Boot threat model at this time is needed.

Change-Id: I41b037b2f5956d327b53cd834345e5aefdcfb5ef
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge "fix(docs): fix `FF-A` substitution" into integration

fix(docs): fix `FF-A` substitution

In this change the `FFA` substitution has been renamed to `FF-A`, as
well as the term it substitutes to - the `FFA` term does not exist.

Change-Id: I0c33d00d82a54

fix(docs): fix `FF-A` substitution

In this change the `FFA` substitution has been renamed to `FF-A`, as
well as the term it substitutes to - the `FFA` term does not exist.

Change-Id: I0c33d00d82a5498f7088e6a2b088a0006dfe7f65
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-c

Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-core AMU auxiliary counters
docs(amu): add AMU documentation
refactor(amu): refactor enablement and context switching
refactor(amu): detect auxiliary counters at runtime
refactor(amu): detect architected counters at runtime
refactor(amu): conditionally compile auxiliary counter support
refactor(amu): factor out register accesses
refactor(amu)!: privatize unused AMU APIs
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
build(amu): introduce `amu.mk`
build(fconf)!: clean up source collection
feat(fdt-wrappers): add CPU enumeration utility function
build(fdt-wrappers): introduce FDT wrappers makefile
build(bl2): deduplicate sources
build(bl1): deduplicate sources

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feat(mpmm): add support for MPMM

MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 a

feat(mpmm): add support for MPMM

MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.

MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.

This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.

Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(amu): add AMU documentation

This change adds some documentation on the AMU and its purpose. This is
expanded on in later patches.

Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01
Signed-of

docs(amu): add AMU documentation

This change adds some documentation on the AMU and its purpose. This is
expanded on in later patches.

Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "Add TRNG Firmware Interface service" into integration

Add TRNG Firmware Interface service

This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and include

Add TRNG Firmware Interface service

This adds the TRNG Firmware Interface Service to the standard
service dispatcher. This includes a method for dispatching entropy
requests to platforms and includes an entropy pool implementation to
avoid dropping any entropy requested from the platform.

Change-Id: I71cadb3cb377a507652eca9e0d68714c973026e9
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "SPCI is now called PSA FF-A" into integration

SPCI is now called PSA FF-A

SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA

SPCI is now called PSA FF-A

SPCI is renamed as PSA FF-A which stands for Platform Security
Architecture Firmware Framework for A class processors.
This patch replaces the occurrence of SPCI with PSA FF-A(in documents)
or simply FFA(in code).

Change-Id: I4ab10adb9ffeef1ff784641dfafd99f515133760
Signed-off-by: J-Alves <joao.alves@arm.com>

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Merge changes from topic "lm/fconf" into integration

* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform

Merge changes from topic "lm/fconf" into integration

* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform io policies into fconf
fconf: Add mbedtls shared heap as property
fconf: Add TBBR disable_authentication property
fconf: Add dynamic config DTBs info as property
fconf: Populate properties from dtb during bl2 setup
fconf: Load config dtb from bl1
fconf: initial commit

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fconf: Add documentation

Change-Id: I606f9491fb6deebc6845c5b9d7db88fc5c895bd9
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

Merge "doc: Add missing terms to the glossary" into integration

doc: Add missing terms to the glossary

Change-Id: Ibca94eae1a9a89c98b4d7cb5b4fd8943bf854030
Signed-off-by: Paul Beesley <paul.beesley@arm.com>

Merge "Added SPCI to the glossary" into integration

Added SPCI to the glossary

Change-Id: I576ae161477f4a69336d15a7741e566bb103124a
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>