Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 ma

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): update mboot threat model with dTPM
docs(tpm): add design documentation for dTPM
fix(rpi3): expose BL1_RW to BL2 map for mboot
feat(rpi3): add dTPM backed measured boot
feat(tpm): add Infineon SLB9670 GPIO SPI config
feat(tpm): add tpm drivers and framework
feat(io): add generic gpio spi bit-bang driver
feat(rpi3): implement eventlog handoff to BL33
feat(rpi3): implement mboot for rpi3

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docs(tpm): add design documentation for dTPM

-documentation for Discrete TPM drivers.
-documentation for a proof of concept on rpi3;
Measured Boot using Discrete TPM.

Signed-off-by: Abhi Singh <ab

docs(tpm): add design documentation for dTPM

-documentation for Discrete TPM drivers.
-documentation for a proof of concept on rpi3;
Measured Boot using Discrete TPM.

Signed-off-by: Abhi Singh <abhi.singh@arm.com>
Change-Id: If8e7c14a1c0b9776af872104aceeff21a13bd821

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Merge changes from topic "gr/lts-doc" into integration

* changes:
docs: updates to LTS
docs: add inital lts doc

docs: add inital lts doc

Ref: https://linaro.atlassian.net/browse/TFC-669

The initial LTS document was created as pdf and was maintained in a
shared folder location, to avoid pdf getting lost and t

docs: add inital lts doc

Ref: https://linaro.atlassian.net/browse/TFC-669

The initial LTS document was created as pdf and was maintained in a
shared folder location, to avoid pdf getting lost and trying to find
where it is we decided to have LTS details part of docs in TF-A.

This patch directly reflects the data from pdf attached to TFC-669.
Any improvements or amends to this will be done at later phases based
on LTS maintainers comments and agreements.

Change-Id: I1434c29f0236161d2a127596e2cc528bf4cc3e85
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): add DPE to RSE desing doc
feat(docs): add RSE provided mboot backends to the threat model
feat(docs): update mboot t

Merge changes from topic "dtpm_poc" into integration

* changes:
feat(docs): add DPE to RSE desing doc
feat(docs): add RSE provided mboot backends to the threat model
feat(docs): update mboot threat model

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feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I23

feat(docs): add RSE provided mboot backends to the threat model

Add CCA Measured Boot and DPE measured boot backends to
the threat model.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Change-Id: I234a2400d00fea606c5312ebddf94e2624463ff8

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feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the poss

feat(docs): update mboot threat model

Restructure Measured Boot threat model for more description and clarity:
- Add what critical assets are to be protected.
- Mention other attributes and the possible attacks.
- Rephrase the section that describes the Measured Boot backends.

Change-Id: I6577a56184992bf16f4aa1b773d1636781cbb049
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level

Merge changes from topic "DPE" into integration

* changes:
feat(tc): group components into certificates
feat(dice): add cert_id argument to dpe_derive_context()
refactor(sds): modify log level for region validity
feat(tc): add dummy TRNG support to be able to boot pVMs
feat(tc): get the parent component provided DPE context_handle
feat(tc): share DPE context handle with child component
feat(tc): add DPE context handle node to device tree
feat(tc): add DPE backend to the measured boot framework
feat(auth): add explicit entries for key OIDs
feat(dice): add DPE driver to measured boot
feat(dice): add client API for DICE Protection Environment
feat(dice): add QCBOR library as a dependency of DPE
feat(dice): add typedefs from the Open DICE repo
docs(changelog): add 'dice' scope
refactor(tc): align image identifier string macros
refactor(fvp): align image identifier string macros
refactor(imx8m): align image identifier string macros
refactor(qemu): align image identifier string macros
fix(measured-boot): add missing image identifier string
refactor(measured-boot): move metadata size macros to a common header
refactor(measured-boot): move image identifier strings to a common header

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feat(dice): add typedefs from the Open DICE repo

The DPE implementation in RSS is aligned with the
Open Profile for DICE specification:
https://pigweed.googlesource.com/open-dice/

Type definitions

feat(dice): add typedefs from the Open DICE repo

The DPE implementation in RSS is aligned with the
Open Profile for DICE specification:
https://pigweed.googlesource.com/open-dice/

Type definitions are needed to specify the input
values for the DPE service. Instead of mandating to
clone the entire open-dice repo, the following file
is copied from the repository:
https://pigweed.googlesource.com/open-dice/+/refs/heads/main/include/dice/dice.h
Git SHA of the source version: cf549422e39da872d64993be944099ac62ba22a9

This is external code, with Apache 2.0 license, therefore
the license.rst is updated accordingly and a copy of this
license is also added.

Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: David Vincze <david.vincze@arm.com>
Change-Id: Ie84b8483034819d1143fe0ec812e66514ac7d4cb

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Merge "docs(threat-model): provide PSR specification reference" into integration

docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I7

docs(threat-model): provide PSR specification reference

Added an assumption in generic threat model that platform's hardware
conforms the Platform Security Requirements specification.

Change-Id: I753287feec1cd459edfd3d1c103e0e701827cc05
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround

Merge changes from topic "srm/Errata_ABI_El3" into integration

* changes:
docs(errata_abi): document the errata abi changes
feat(fvp): enable errata management interface
fix(cpus): workaround platforms non-arm interconnect
refactor(errata_abi): factor in non-arm interconnect
feat(errata_abi): errata management firmware interface

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docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Chan

docs(errata_abi): document the errata abi changes

Updated errata ABI feature enable flag and the errata non-arm
interconnect based flag, the default values for when the
feature is not enabled.

Change-Id: Ieb2144a1bc38f4ed684fda8280842a18964ba148
Signed-off-by: Sona Mathew <SonaRebecca.Mathew@arm.com>

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Merge "docs: fix a typo in the glossary" into integration

docs: fix a typo in the glossary

Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
Change-Id: I4c76fde5e487ab4b2495f1ea692ae07f8be81d57

Merge "docs(threat-model): add a notes related to the Measured Boot" into integration

docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measur

docs(threat-model): add a notes related to the Measured Boot

TF-A currently does not have any TPM2 driver for extending
measurements into a discrete TPM chip. In TPM-based attestation
scheme, measurements are just stored into a TCG-compatible event
log buffer in secure memory.

In light of the fact that Event Log measurements are taken by BL1 and
BL2, we need to trust these components to store genuine measurements,
and the Generic Threat Model always mitigates against attacks on these
components, therefore, there is no explicit document for the Measured
Boot threat model at this time is needed.

Change-Id: I41b037b2f5956d327b53cd834345e5aefdcfb5ef
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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Merge changes from topic "ffa_el3_spmc" into integration

* changes:
docs(spm): add threat model for el3 spmc
docs(spm): add design documentation

docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Cha

docs(spm): add threat model for el3 spmc

Threat model for EL3 SPMC.
The mitigations are based on the guidance
provided in FF-A v1.1 EAC0 spec.

Signed-off-by: Shruti Gupta <shruti.gupta@arm.com>
Change-Id: I7f4c9370b6eefe6d1a7d1afac27e8b3a7b476072

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Merge changes from topic "mb/drtm-preparatory-patches" into integration

* changes:
docs(drtm): steps to run DRTM implementation
docs(drtm): add platform APIs for DRTM
feat(drtm): flush dcache

Merge changes from topic "mb/drtm-preparatory-patches" into integration

* changes:
docs(drtm): steps to run DRTM implementation
docs(drtm): add platform APIs for DRTM
feat(drtm): flush dcache before DLME launch
feat(drtm): invalidate icache before DLME launch
feat(drtm): ensure that passed region lies within Non-Secure region of DRAM
feat(fvp): add plat API to validate that passed region is non-secure
feat(drtm): ensure that no SDEI event registered during dynamic launch
feat(drtm): prepare EL state during dynamic launch
feat(drtm): prepare DLME data for DLME launch
feat(drtm): take DRTM components measurements before DLME launch
feat(drtm): add a few DRTM DMA protection APIs
feat(drtm): add remediation driver support in DRTM
feat(fvp): add plat API to set and get the DRTM error
feat(drtm): add Event Log driver support for DRTM
feat(drtm): check drtm arguments during dynamic launch
feat(drtm): introduce drtm dynamic launch function
refactor(measured-boot): split out a few Event Log driver functions
feat(drtm): retrieve DRTM features
feat(drtm): add platform functions for DRTM
feat(sdei): add a function to return total number of events registered
feat(drtm): add PCR entries for DRTM
feat(drtm): update drtm setup function
refactor(crypto): change CRYPTO_SUPPORT flag to numeric
feat(mbedtls): update mbedTLS driver for DRTM support
feat(fvp): add crypto support in BL31
feat(crypto): update crypto module for DRTM support
build(changelog): add new scope for mbedTLS and Crypto module
feat(drtm): add standard DRTM service
build(changelog): add new scope for DRTM service
feat(fvp): increase MAX_XLAT_TABLES entries for DRTM support
feat(fvp): increase BL31's stack size for DRTM support
feat(fvp): add platform hooks for DRTM DMA protection

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docs(drtm): steps to run DRTM implementation

Documented steps to run DRTM implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610

docs(drtm): steps to run DRTM implementation

Documented steps to run DRTM implementation.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I30dd8c1088a54a8906389c2584d922862610dae0

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Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-c

Merge changes from topic "ck/mpmm" into integration

* changes:
docs(maintainers): add Chris Kay to AMU and MPMM
feat(tc): enable MPMM
feat(mpmm): add support for MPMM
feat(amu): enable per-core AMU auxiliary counters
docs(amu): add AMU documentation
refactor(amu): refactor enablement and context switching
refactor(amu): detect auxiliary counters at runtime
refactor(amu): detect architected counters at runtime
refactor(amu): conditionally compile auxiliary counter support
refactor(amu): factor out register accesses
refactor(amu)!: privatize unused AMU APIs
refactor(amu)!: remove `PLAT_AMU_GROUP1_COUNTERS_MASK`
build(amu): introduce `amu.mk`
build(fconf)!: clean up source collection
feat(fdt-wrappers): add CPU enumeration utility function
build(fdt-wrappers): introduce FDT wrappers makefile
build(bl2): deduplicate sources
build(bl1): deduplicate sources

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feat(mpmm): add support for MPMM

MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 a

feat(mpmm): add support for MPMM

MPMM - the Maximum Power Mitigation Mechanism - is an optional
microarchitectural feature present on some Armv9-A cores, introduced
with the Cortex-X2, Cortex-A710 and Cortex-A510 cores.

MPMM allows the SoC firmware to detect and limit high activity events
to assist in SoC processor power domain dynamic power budgeting and
limit the triggering of whole-rail (i.e. clock chopping) responses to
overcurrent conditions.

This feature is enabled via the `ENABLE_MPMM` build option.
Configuration can be done via FCONF by enabling `ENABLE_MPMM_FCONF`, or
by via the plaform-implemented `plat_mpmm_topology` function.

Change-Id: I77da82808ad4744ece8263f0bf215c5a091c3167
Signed-off-by: Chris Kay <chris.kay@arm.com>

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docs(amu): add AMU documentation

This change adds some documentation on the AMU and its purpose. This is
expanded on in later patches.

Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01
Signed-of

docs(amu): add AMU documentation

This change adds some documentation on the AMU and its purpose. This is
expanded on in later patches.

Change-Id: If2834676790938d8da5ea2ceba37b674f6cc0f01
Signed-off-by: Chris Kay <chris.kay@arm.com>

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Merge "docs(ff-a): fix specification naming" into integration