1Glossary 2======== 3 4This glossary provides definitions for terms and abbreviations used in the TF-A 5documentation. 6 7You can find additional definitions in the `Arm Glossary`_. 8 9.. glossary:: 10 :sorted: 11 12 AArch32 13 32-bit execution state of the ARMv8 ISA 14 15 AArch64 16 64-bit execution state of the ARMv8 ISA 17 18 AMU 19 Activity Monitor Unit, a hardware monitoring unit introduced by FEAT_AMUv1 20 that exposes CPU core runtime metrics as a set of counter registers. 21 22 API 23 Application Programming Interface 24 25 AT 26 Address Translation 27 28 BTI 29 Branch Target Identification. An Armv8.5 extension providing additional 30 control flow integrity around indirect branches and their targets. 31 32 CoT 33 COT 34 Chain of Trust 35 36 CSS 37 Compute Sub-System 38 39 CRB 40 Command Response Buffer 41 42 CVE 43 Common Vulnerabilities and Exposures. A CVE document is commonly used to 44 describe a publicly-known security vulnerability. 45 46 DICE 47 Device Identifier Composition Engine 48 49 DCE 50 DRTM Configuration Environment 51 52 D-CRTM 53 Dynamic Code Root of Trust for Measurement 54 55 DLME 56 Dynamically Launched Measured Environment 57 58 DRTM 59 Dynamic Root of Trust for Measurement 60 61 DPE 62 DICE Protection Environment 63 64 DS-5 65 Arm Development Studio 5 66 67 DSU 68 DynamIQ Shared Unit 69 70 DT 71 Device Tree 72 73 DTB 74 Device Tree Blob 75 76 EL 77 Exception Level 78 79 EHF 80 Exception Handling Framework 81 82 ERRATA_ABI 83 Errata management firmware interface 84 85 FCONF 86 Firmware Configuration Framework 87 88 FDT 89 Flattened Device Tree 90 91 FF-A 92 Firmware Framework for Arm A-profile 93 94 FIFO 95 First In, First Out 96 97 FIP 98 Firmware Image Package 99 100 FVP 101 Fixed Virtual Platform 102 103 FWU 104 FirmWare Update 105 106 GIC 107 Generic Interrupt Controller 108 109 HES 110 Arm CCA Hardware Enforced Security 111 112 I2C 113 Inter-Integrated Circuit Protocol 114 115 ISA 116 Instruction Set Architecture 117 118 Linaro 119 A collaborative engineering organization consolidating 120 and optimizing open source software and tools for the Arm architecture. 121 122 LSP 123 A logical secure partition managed by SPM 124 125 MMU 126 Memory Management Unit 127 128 MPAM 129 Memory Partitioning And Monitoring. An optional Armv8.4 extension. 130 131 MPMM 132 Maximum Power Mitigation Mechanism, an optional power management mechanism 133 supported by some Arm Armv9-A cores. 134 135 MPIDR 136 Multiprocessor Affinity Register 137 138 MTE 139 Memory Tagging Extension. An optional Armv8.5 extension that enables 140 hardware-assisted memory tagging. 141 142 LTS 143 Long-Term Support 144 145 OEN 146 Owning Entity Number 147 148 OP-TEE 149 Open Portable Trusted Execution Environment. An example of a :term:`TEE` 150 151 OTE 152 Open-source Trusted Execution Environment 153 154 PCR 155 Platform Configuration Register 156 157 PDD 158 Platform Design Document 159 160 PAUTH 161 Pointer Authentication. An optional extension introduced in Armv8.3. 162 163 PMF 164 Performance Measurement Framework 165 166 PSA 167 Platform Security Architecture 168 169 PSR 170 Platform Security Requirements 171 172 PSCI 173 Power State Coordination Interface 174 175 RAS 176 Reliability, Availability, and Serviceability extensions. A mandatory 177 extension for the Armv8.2 architecture and later. An optional extension to 178 the base Armv8 architecture. 179 180 ROT 181 Root of Trust 182 183 RSE 184 Runtime Security Engine 185 186 SCMI 187 System Control and Management Interface 188 189 SCP 190 System Control Processor 191 192 SDEI 193 Software Delegated Exception Interface 194 195 SDS 196 Shared Data Storage 197 198 SEA 199 Synchronous External Abort 200 201 SiP 202 SIP 203 Silicon Provider 204 205 SMC 206 Secure Monitor Call 207 208 SMCCC 209 :term:`SMC` Calling Convention 210 211 SoC 212 System on Chip 213 214 SP 215 Secure Partition 216 217 SPD 218 Secure Payload Dispatcher 219 220 SPM 221 Secure Partition Manager 222 223 SPI 224 Serial Peripheral Interface 225 226 SRTM 227 Static Root of Trust for Measurement 228 229 SSBS 230 Speculative Store Bypass Safe. Introduced in Armv8.5, this configuration 231 bit can be set by software to allow or prevent the hardware from 232 performing speculative operations. 233 234 SVE 235 Scalable Vector Extension 236 237 TBB 238 Trusted Board Boot 239 240 TBBR 241 Trusted Board Boot Requirements 242 243 TCB 244 Trusted Compute Base 245 246 TCG 247 Trusted Computing Group 248 249 TEE 250 Trusted Execution Environment 251 252 TF-A 253 Trusted Firmware-A 254 255 TF-M 256 Trusted Firmware-M 257 258 TLB 259 Translation Lookaside Buffer 260 261 TLK 262 Trusted Little Kernel. A Trusted OS from NVIDIA. 263 264 TPM 265 Trusted Platform Module 266 267 TRNG 268 True Random Number Generator (hardware based) 269 270 TSP 271 Test Secure Payload 272 273 TZC 274 TrustZone Controller 275 276 UBSAN 277 Undefined Behavior Sanitizer 278 279 UEFI 280 Unified Extensible Firmware Interface 281 282 WDOG 283 Watchdog 284 285 XLAT 286 Translation (abbr.). For example, "XLAT table". 287 288.. _`Arm Glossary`: https://developer.arm.com/support/arm-glossary 289