| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/ |
| H A D | rdaspen_topology.c | 29 #if PLATFORM_CORE_COUNT > 1
32 #if PLATFORM_CORE_COUNT > 2
35 #if PLATFORM_CORE_COUNT > 3
38 #if PLATFORM_CORE_COUNT > 4
41 #if PLATFORM_CORE_COUNT > 5
44 #if PLATFORM_CORE_COUNT > 6
47 #if PLATFORM_CORE_COUNT > 7
50 #if PLATFORM_CORE_COUNT > 8
53 #if PLATFORM_CORE_COUNT > 9
56 #if PLATFORM_CORE_COUNT > 10
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| /rk3399_ARM-atf/plat/arm/board/automotive_rd/platform/rdaspen/include/ |
| H A D | platform_def.h | 41 #ifndef PLATFORM_CORE_COUNT
42 #define PLATFORM_CORE_COUNT U(16) macro
45 #if (PLATFORM_CORE_COUNT > 16) || (PLATFORM_CORE_COUNT < 1)
49 #if (PLATFORM_CORE_COUNT <= 4)
50 #define PLATFORM_CLUSTER_0_CORE_COUNT U(PLATFORM_CORE_COUNT)
58 #if (PLATFORM_CORE_COUNT <= 8)
59 #define PLATFORM_CLUSTER_1_CORE_COUNT U(PLATFORM_CORE_COUNT - 4)
66 #if (PLATFORM_CORE_COUNT <= 12)
67 #define PLATFORM_CLUSTER_2_CORE_COUNT U(PLATFORM_CORE_COUNT - 8)
72 #define PLATFORM_CLUSTER_3_CORE_COUNT U(PLATFORM_CORE_COUNT - 12)
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| /rk3399_ARM-atf/plat/ti/common/ |
| H A D | k3_gicv3.c | 20 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
22 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
36 .rdistif_num = PLATFORM_CORE_COUNT,
97 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_save_context()
106 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_restore_context()
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| /rk3399_ARM-atf/plat/mediatek/drivers/gicv3/ |
| H A D | mt_gic_v3.c | 24 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
26 static gicv3_redist_ctx_t rdist_ctx[PLATFORM_CORE_COUNT];
42 .rdistif_num = PLATFORM_CORE_COUNT,
80 for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { in gicr_get_sgi_pending()
114 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) in mt_gic_rdistif_save()
128 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) in mt_gic_rdistif_restore()
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| /rk3399_ARM-atf/plat/nxp/s32/s32g274ardb2/ |
| H A D | s32g2_soc.c | 15 PLATFORM_CORE_COUNT / U(2), in plat_get_power_domain_tree_desc()
16 PLATFORM_CORE_COUNT / U(2), in plat_get_power_domain_tree_desc()
42 if (core_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/socionext/uniphier/ |
| H A D | uniphier_gicv3.c | 17 static uintptr_t uniphier_rdistif_base_addrs[PLATFORM_CORE_COUNT];
65 .rdistif_num = PLATFORM_CORE_COUNT,
74 .rdistif_num = PLATFORM_CORE_COUNT,
83 .rdistif_num = PLATFORM_CORE_COUNT,
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| /rk3399_ARM-atf/plat/allwinner/common/include/ |
| H A D | platform_def.h | 68 PLATFORM_CORE_COUNT)
73 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ macro
76 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | plat_imx8_gic.c | 25 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
46 .rdistif_num = PLATFORM_CORE_COUNT,
132 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_save()
141 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_restore()
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| /rk3399_ARM-atf/plat/hisilicon/poplar/ |
| H A D | plat_topology.c | 16 PLATFORM_CORE_COUNT,
29 if ((mpidr & MPIDR_CPU_MASK) >= PLATFORM_CORE_COUNT) in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/mediatek/drivers/gic600/ |
| H A D | mt_gic_v3.c | 24 uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
25 static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
44 .rdistif_num = PLATFORM_CORE_COUNT,
61 unsigned int saved_sgi[PLATFORM_CORE_COUNT];
63 unsigned int saved_prio[PLATFORM_CORE_COUNT][GICR_NUM_REGS(IPRIORITYR)];
169 for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { in mt_gic_rdistif_restore_all()
195 for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { in gic_sgi_save_all()
207 for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) { in gic_sgi_restore_all()
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| /rk3399_ARM-atf/plat/mediatek/include/armv8_2/ |
| H A D | arch_def.h | 18 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) macro
22 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/mediatek/include/armv9/ |
| H A D | arch_def.h | 25 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT) macro
29 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/arm/board/morello/ |
| H A D | morello_topology.c | 11 CASSERT(PLATFORM_CORE_COUNT == 4U, assert_invalid_platform_core_count);
59 const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
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| /rk3399_ARM-atf/plat/rpi/rpi4/include/ |
| H A D | platform_def.h | 25 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT macro
31 PLATFORM_CORE_COUNT)
89 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/rpi/rpi5/include/ |
| H A D | platform_def.h | 26 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT macro
32 PLATFORM_CORE_COUNT)
90 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/st/stm32mp2/ |
| H A D | stm32mp2_topology.c | 15 PLATFORM_CORE_COUNT,
52 if (cpu_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_topology.c | 15 PLATFORM_CORE_COUNT,
52 if (cpu_id >= PLATFORM_CORE_COUNT) { in plat_core_pos_by_mpidr()
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| /rk3399_ARM-atf/plat/qti/msm8916/ |
| H A D | msm8916_config.c | 44 #if PLATFORM_CORE_COUNT > 1
69 if (PLATFORM_CORE_COUNT > 1) { in msm8916_configure_apcs_cluster()
161 if (PLATFORM_CORE_COUNT > 1) { in msm8916_configure_smmu()
177 if (PLATFORM_CORE_COUNT > 1) { in msm8916_configure_smmu()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/include/ |
| H A D | platform_def.h | 33 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ macro
36 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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| /rk3399_ARM-atf/plat/amlogic/gxl/include/ |
| H A D | platform_def.h | 23 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT macro
29 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/amlogic/g12a/include/ |
| H A D | platform_def.h | 23 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT macro
29 PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/qemu/common/ |
| H A D | qemu_gicv3.c | 17 static uintptr_t qemu_rdistif_base_addrs[PLATFORM_CORE_COUNT];
29 .rdistif_num = PLATFORM_CORE_COUNT,
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| /rk3399_ARM-atf/include/plat/nuvoton/npcm845x/ |
| H A D | platform_def.h | 31 #define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT macro
54 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
69 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
275 (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT)
282 (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT)
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| /rk3399_ARM-atf/plat/nvidia/tegra/common/ |
| H A D | tegra_gicv3.c | 19 static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
42 tegra_gic_data.rdistif_num = PLATFORM_CORE_COUNT; in tegra_gic_setup()
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| /rk3399_ARM-atf/plat/amlogic/gxbb/include/ |
| H A D | platform_def.h | 26 #define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT macro
32 PLATFORM_CORE_COUNT)
|