1*dfd5bfb0SChandni Cherukuri /*
2*dfd5bfb0SChandni Cherukuri * Copyright (c) 2020, Arm Limited. All rights reserved.
3*dfd5bfb0SChandni Cherukuri *
4*dfd5bfb0SChandni Cherukuri * SPDX-License-Identifier: BSD-3-Clause
5*dfd5bfb0SChandni Cherukuri */
6*dfd5bfb0SChandni Cherukuri
7*dfd5bfb0SChandni Cherukuri #include <lib/cassert.h>
8*dfd5bfb0SChandni Cherukuri #include <plat/arm/common/plat_arm.h>
9*dfd5bfb0SChandni Cherukuri
10*dfd5bfb0SChandni Cherukuri /* Compile time assertion to ensure the core count is 4 */
11*dfd5bfb0SChandni Cherukuri CASSERT(PLATFORM_CORE_COUNT == 4U, assert_invalid_platform_core_count);
12*dfd5bfb0SChandni Cherukuri
13*dfd5bfb0SChandni Cherukuri /* Topology */
14*dfd5bfb0SChandni Cherukuri typedef struct morello_topology {
15*dfd5bfb0SChandni Cherukuri const unsigned char *power_tree;
16*dfd5bfb0SChandni Cherukuri unsigned int plat_cluster_core_count;
17*dfd5bfb0SChandni Cherukuri } morello_topology_t;
18*dfd5bfb0SChandni Cherukuri
19*dfd5bfb0SChandni Cherukuri /*
20*dfd5bfb0SChandni Cherukuri * The power domain tree descriptor. The cluster power domains are
21*dfd5bfb0SChandni Cherukuri * arranged so that when the PSCI generic code creates the power domain tree,
22*dfd5bfb0SChandni Cherukuri * the indices of the CPU power domain nodes it allocates match the linear
23*dfd5bfb0SChandni Cherukuri * indices returned by plat_core_pos_by_mpidr().
24*dfd5bfb0SChandni Cherukuri */
25*dfd5bfb0SChandni Cherukuri const unsigned char morello_pd_tree_desc[] = {
26*dfd5bfb0SChandni Cherukuri PLAT_MORELLO_CHIP_COUNT,
27*dfd5bfb0SChandni Cherukuri PLAT_ARM_CLUSTER_COUNT,
28*dfd5bfb0SChandni Cherukuri MORELLO_MAX_CPUS_PER_CLUSTER,
29*dfd5bfb0SChandni Cherukuri MORELLO_MAX_CPUS_PER_CLUSTER,
30*dfd5bfb0SChandni Cherukuri };
31*dfd5bfb0SChandni Cherukuri
32*dfd5bfb0SChandni Cherukuri /* Topology configuration for morello */
33*dfd5bfb0SChandni Cherukuri const morello_topology_t morello_topology = {
34*dfd5bfb0SChandni Cherukuri .power_tree = morello_pd_tree_desc,
35*dfd5bfb0SChandni Cherukuri .plat_cluster_core_count = MORELLO_MAX_CPUS_PER_CLUSTER
36*dfd5bfb0SChandni Cherukuri };
37*dfd5bfb0SChandni Cherukuri
38*dfd5bfb0SChandni Cherukuri /*******************************************************************************
39*dfd5bfb0SChandni Cherukuri * This function returns the topology tree information.
40*dfd5bfb0SChandni Cherukuri ******************************************************************************/
plat_get_power_domain_tree_desc(void)41*dfd5bfb0SChandni Cherukuri const unsigned char *plat_get_power_domain_tree_desc(void)
42*dfd5bfb0SChandni Cherukuri {
43*dfd5bfb0SChandni Cherukuri return morello_topology.power_tree;
44*dfd5bfb0SChandni Cherukuri }
45*dfd5bfb0SChandni Cherukuri
46*dfd5bfb0SChandni Cherukuri /*******************************************************************************
47*dfd5bfb0SChandni Cherukuri * This function returns the core count within the cluster corresponding to
48*dfd5bfb0SChandni Cherukuri * `mpidr`.
49*dfd5bfb0SChandni Cherukuri ******************************************************************************/
plat_arm_get_cluster_core_count(u_register_t mpidr)50*dfd5bfb0SChandni Cherukuri unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr)
51*dfd5bfb0SChandni Cherukuri {
52*dfd5bfb0SChandni Cherukuri return morello_topology.plat_cluster_core_count;
53*dfd5bfb0SChandni Cherukuri }
54*dfd5bfb0SChandni Cherukuri
55*dfd5bfb0SChandni Cherukuri /*******************************************************************************
56*dfd5bfb0SChandni Cherukuri * The array mapping platform core position (implemented by plat_my_core_pos())
57*dfd5bfb0SChandni Cherukuri * to the SCMI power domain ID implemented by SCP.
58*dfd5bfb0SChandni Cherukuri ******************************************************************************/
59*dfd5bfb0SChandni Cherukuri const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[PLATFORM_CORE_COUNT] = {
60*dfd5bfb0SChandni Cherukuri 0, 1, 2, 3};
61