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Searched refs:MAP_REGION_FLAT (Results 1 – 25 of 138) sorted by relevance

123456

/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.c22 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
24 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
26 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
30 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
32 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
34 MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
36 MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
38 MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
40 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE,
[all …]
/rk3399_ARM-atf/include/plat/brcm/common/
H A Dbrcm_def.h55 #define BRCM_MAP_SHARED_RAM MAP_REGION_FLAT( \
60 #define BRCM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
66 #define BRCM_MAP_NS_SHARED_DRAM MAP_REGION_FLAT( \
73 #define BRCM_MAP_EXT_SRAM MAP_REGION_FLAT( \
79 #define BRCM_MAP_NAND_RO MAP_REGION_FLAT(NAND_BASE_ADDR,\
83 #define BRCM_MAP_QSPI_RO MAP_REGION_FLAT(QSPI_BASE_ADDR,\
87 #define HSLS_REGION MAP_REGION_FLAT(HSLS_BASE_ADDR, \
91 #define CCN_REGION MAP_REGION_FLAT(PLAT_BRCM_CCN_BASE, \
95 #define GIC500_REGION MAP_REGION_FLAT(GIC500_BASE, \
99 #define PERIPH0_REGION MAP_REGION_FLAT(PERIPH0_BASE, \
[all …]
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
27 #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
35 #define MAP_HDCP_RX MAP_REGION_FLAT(AML_HDCP_RX_BASE, \
39 #define MAP_HDCP_TX MAP_REGION_FLAT(AML_HDCP_TX_BASE, \
43 #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
47 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
51 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
55 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
[all …]
/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NS_SHARE_MEM MAP_REGION_FLAT(AML_NS_SHARE_MEM_BASE, \
27 #define MAP_SEC_SHARE_MEM MAP_REGION_FLAT(AML_SEC_SHARE_MEM_BASE, \
31 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
35 #define MAP_GIC_DEVICE MAP_REGION_FLAT(AML_GIC_DEVICE_BASE, \
39 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
43 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
47 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
66 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
70 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_setup.c73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
75 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
77 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
81 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
83 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
85 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
87 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
89 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
[all …]
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
27 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
31 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
35 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
39 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
43 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
61 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
65 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
[all …]
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_common.c19 #define MAP_NSDRAM0 MAP_REGION_FLAT(AML_NSDRAM0_BASE, \
23 #define MAP_NSDRAM1 MAP_REGION_FLAT(AML_NSDRAM1_BASE, \
27 #define MAP_SEC_DEVICE0 MAP_REGION_FLAT(AML_SEC_DEVICE0_BASE, \
31 #define MAP_SEC_DEVICE1 MAP_REGION_FLAT(AML_SEC_DEVICE1_BASE, \
35 #define MAP_TZRAM MAP_REGION_FLAT(AML_TZRAM_BASE, \
39 #define MAP_SEC_DEVICE2 MAP_REGION_FLAT(AML_SEC_DEVICE2_BASE, \
43 #define MAP_SEC_DEVICE3 MAP_REGION_FLAT(AML_SEC_DEVICE3_BASE, \
61 #define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
65 #define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
29 MAP_REGION_FLAT(TZPC_BASE, TZPC_SIZE,
31 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
33 MAP_REGION_FLAT(SRAM_BASE, SRAM_SIZE,
35 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
37 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
39 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
41 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8195/aarch64/
H A Dplatform_common.c14 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
16 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
18 MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
20 MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
22 MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
24 MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
26 MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
28 MAP_REGION_FLAT(APUSYS_APU_PLL_BASE, APUSYS_APU_PLL_SIZE,
30 MAP_REGION_FLAT(APUSYS_APU_ACC_BASE, APUSYS_APU_ACC_SIZE,
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/
H A Dnrd_css_fw_def3.h65 MAP_REGION_FLAT( \
72 MAP_REGION_FLAT( \
79 MAP_REGION_FLAT( \
85 MAP_REGION_FLAT( \
91 MAP_REGION_FLAT( \
97 MAP_REGION_FLAT( \
103 MAP_REGION_FLAT( \
109 MAP_REGION_FLAT( \
116 MAP_REGION_FLAT( \
136 #define NRD_CSS_MAP_BL31_DTB MAP_REGION_FLAT( \
/rk3399_ARM-atf/plat/mediatek/mt8192/aarch64/
H A Dplatform_common.c16 MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
18 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
20 MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
22 MAP_REGION_FLAT(MTK_MCDI_SRAM_BASE, MTK_MCDI_SRAM_MAP_SIZE,
24 MAP_REGION_FLAT(APUSYS_SCTRL_REVISER_BASE, APUSYS_SCTRL_REVISER_SIZE,
26 MAP_REGION_FLAT(APUSYS_APU_S_S_4_BASE, APUSYS_APU_S_S_4_SIZE,
28 MAP_REGION_FLAT(APUSYS_APC_AO_WRAPPER_BASE, APUSYS_APC_AO_WRAPPER_SIZE,
30 MAP_REGION_FLAT(APUSYS_NOC_DAPC_AO_BASE, APUSYS_NOC_DAPC_AO_SIZE,
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd2/
H A Dnrd_ros_fw_def2.h21 MAP_REGION_FLAT( \
29 MAP_REGION_FLAT( \
36 MAP_REGION_FLAT( \
42 MAP_REGION_FLAT( \
49 MAP_REGION_FLAT( \
55 MAP_REGION_FLAT( \
62 MAP_REGION_FLAT( \
/rk3399_ARM-atf/plat/renesas/rcar_gen5/aarch64/
H A Dplatform_common.c27 MAP_REGION_FLAT(PARAMS_BASE, PARAMS_SIZE, \
31 MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, RCAR_SHARED_MEM_SIZE, \
35 MAP_REGION_FLAT(DEVICE_RCAR_BASE1, DEVICE_RCAR_SIZE1, \
39 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, DEVICE_RCAR_SIZE2, \
43 MAP_REGION_FLAT(DEVICE_RCAR_BASE3, DEVICE_RCAR_SIZE3, \
47 MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, RCAR_BL31_CRASH_SIZE, \
51 MAP_REGION_FLAT(DEVICE_SRAM_BASE, DEVICE_SRAM_SIZE, \
55 MAP_REGION_FLAT(DEVICE_SRAM_DATA_BASE, \
60 MAP_REGION_FLAT(RCAR_SCMI_CHANNEL_MMU_BASE, \
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_setup.c89 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x4000U, /* 16KB */
91 MAP_REGION_FLAT(TEGRA_GPCDMA_BASE, 0x10000U, /* 64KB */
93 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x8000U, /* 32KB */
95 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
98 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
100 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
102 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
105 MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x2000U, /* 8KB */
107 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x1000, /* 4KB */
109 MAP_REGION_FLAT(TEGRA_GICC_BASE, 0x1000, /* 4KB */
[all …]
/rk3399_ARM-atf/plat/mediatek/mt8196/
H A Dplat_mmap.c14 MAP_REGION_FLAT(MT_GIC_BASE, MTK_GIC_REG_SIZE,
16 MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
18 MAP_REGION_FLAT(DP_SEC_BASE, DP_SEC_SIZE,
20 MAP_REGION_FLAT(EDP_SEC_BASE, EDP_SEC_SIZE,
22 MAP_REGION_FLAT(APU_MBOX0, APU_MBOX0_SZ,
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c36 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
38 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
40 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
42 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
44 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
46 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
48 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
95 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
97 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl2_el3_plat_arch_setup()
99 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
[all …]
H A Dbl31_plat_setup.c140 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
142 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
144 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
146 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
148 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
150 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
152 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
164 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, in bl31_plat_arch_setup()
166 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
168 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
[all …]
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c40 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
42 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
44 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
46 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
48 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
50 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
52 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
100 MAP_REGION_FLAT(BL2_BASE, BL2_END - BL2_BASE, in bl2_el3_plat_arch_setup()
102 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl2_el3_plat_arch_setup()
104 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
[all …]
/rk3399_ARM-atf/plat/intel/soc/n5x/
H A Dbl31_plat_setup.c133 MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE,
135 MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE,
137 MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE,
139 MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE,
141 MAP_REGION_FLAT(DEVICE3_BASE, DEVICE3_SIZE,
143 MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE,
145 MAP_REGION_FLAT(DEVICE4_BASE, DEVICE4_SIZE,
157 MAP_REGION_FLAT(BL31_BASE, BL31_END - BL31_BASE, in bl31_plat_arch_setup()
159 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
161 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.c21 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE,
23 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE,
25 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE,
27 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE,
29 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
31 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
33 MAP_REGION_FLAT(UART0_BASE, UART0_SIZE,
35 MAP_REGION_FLAT(UART1_BASE, UART1_SIZE,
37 MAP_REGION_FLAT(UART2_BASE, UART2_SIZE,
39 MAP_REGION_FLAT(UART3_BASE, UART3_SIZE,
[all …]
/rk3399_ARM-atf/plat/renesas/common/aarch64/
H A Dplatform_common.c39 #define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
43 #define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
47 #define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
51 #define MAP_DEVICE_RCAR MAP_REGION_FLAT(DEVICE_RCAR_BASE, \
55 #define MAP_DEVICE_RCAR2 MAP_REGION_FLAT(DEVICE_RCAR_BASE2, \
59 #define MAP_SRAM MAP_REGION_FLAT(DEVICE_SRAM_BASE, \
63 #define MAP_SRAM_STACK MAP_REGION_FLAT(DEVICE_SRAM_STACK_BASE, \
67 #define MAP_ATFW_CRASH MAP_REGION_FLAT(RCAR_BL31_CRASH_BASE, \
71 #define MAP_ATFW_LOG MAP_REGION_FLAT(RCAR_BL31_LOG_BASE, \
75 #define MAP_DRAM0 MAP_REGION_FLAT(DRAM1_BASE, \
[all …]
/rk3399_ARM-atf/plat/imx/imx9/imx94/include/
H A Dplatform_def.h110 #define AIPS2_MAP MAP_REGION_FLAT(AIPS2_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW)
111 #define AIPS3_MAP MAP_REGION_FLAT(AIPS3_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW)
112 #define GIC_MAP MAP_REGION_FLAT(PLAT_GICD_BASE, 0x200000, MT_DEVICE | MT_RW)
113 #define AIPS1_MAP MAP_REGION_FLAT(AIPS1_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW)
114 #define GPIO2_MAP MAP_REGION_FLAT(GPIO2_BASE, 0x20000, MT_DEVICE | MT_RW)
115 #define GPIO4_MAP MAP_REGION_FLAT(GPIO4_BASE, 0x20000, MT_DEVICE | MT_RW)
116 #define GPIO6_MAP MAP_REGION_FLAT(GPIO6_BASE, 0x20000, MT_DEVICE | MT_RW)
117 #define ELE_MU_MAP MAP_REGION_FLAT(ELE_MU_BASE, 0x10000, MT_DEVICE | MT_RW)
118 #define AIPS4_MAP MAP_REGION_FLAT(AIPS4_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW)
/rk3399_ARM-atf/include/plat/nuvoton/common/
H A Dnpcm845x_arm_def.h182 #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
191 #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
246 #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
254 #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
259 #define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \
265 #define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \
271 #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
275 #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
280 #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
286 #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
[all …]
/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dimx8mq_bl31_setup.c49 MAP_REGION_FLAT(GPV_BASE, GPV_SIZE, MT_DEVICE | MT_RW), /* GPV map */
50 MAP_REGION_FLAT(IMX_ROM_BASE, IMX_ROM_SIZE, MT_MEMORY | MT_RO), /* ROM map */
51 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
52 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW), /* GIC map */
53 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX map */
54 MAP_REGION_FLAT(IMX_DRAM_BASE, IMX_DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
55 MAP_REGION_FLAT(IMX_CAAM_RAM_BASE, IMX_CAAM_RAM_SIZE, MT_MEMORY | MT_RW), /* CAMM RAM */
56 MAP_REGION_FLAT(IMX_NS_OCRAM_BASE, IMX_NS_OCRAM_SIZE, MT_MEMORY | MT_RW), /* NS OCRAM */
212 MAP_REGION_FLAT(BL31_START, BL31_SIZE, in bl31_plat_arch_setup()
214 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, in bl31_plat_arch_setup()
[all …]
/rk3399_ARM-atf/include/plat/arm/board/common/
H A Dv2m_def.h124 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\
128 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
132 #define V2M_MAP_FLASH1_RW MAP_REGION_FLAT(V2M_FLASH1_BASE,\
136 #define V2M_MAP_FLASH1_RO MAP_REGION_FLAT(V2M_FLASH1_BASE,\
140 #define V2M_MAP_IOFPGA MAP_REGION_FLAT(V2M_IOFPGA_BASE,\
145 #define V2M_MAP_IOFPGA_EL0 MAP_REGION_FLAT( \
150 #define V2M_MAP_SECURE_SYSTEMREG_EL0 MAP_REGION_FLAT( \
155 #define V2M_MAP_FLASH0_RW_EL0 MAP_REGION_FLAT( \
160 #define V2M_MAP_FLASH1_RW_EL0 MAP_REGION_FLAT( \

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