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Searched refs:BL_RO_DATA_BASE (Results 1 – 25 of 44) sorted by relevance

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/rk3399_ARM-atf/plat/socionext/synquacer/
H A Dsq_xlat_setup.c33 (void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END); in sq_mmap_setup()
34 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, in sq_mmap_setup()
35 round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE, in sq_mmap_setup()
/rk3399_ARM-atf/plat/mediatek/include/
H A Dmtk_mmap_pool.h47 BL_RO_DATA_BASE, \
48 BL_RO_DATA_END - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/qti/msm8916/
H A Dmsm8916_setup.c107 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, in msm8916_plat_arch_setup()
108 BL_RO_DATA_END - BL_RO_DATA_BASE, in msm8916_plat_arch_setup()
/rk3399_ARM-atf/plat/xilinx/common/tsp/
H A Dtsp_plat_setup.c78 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, in tsp_plat_arch_setup()
/rk3399_ARM-atf/include/plat/common/
H A Dcommon_def.h139 #define BL1_RO_DATA_BASE BL_RO_DATA_BASE
143 #define BL2_RO_DATA_BASE BL_RO_DATA_BASE
147 #define BL_RO_DATA_BASE UL(0) macro
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_common.c43 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, in sunxi_configure_mmu_el3()
44 BL_RO_DATA_END - BL_RO_DATA_BASE, in sunxi_configure_mmu_el3()
/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_common.c74 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
75 BL_RO_DATA_END - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_common.c69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
70 BL_RO_DATA_END - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_common.c69 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
70 BL_RO_DATA_END - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_common.c84 #define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
85 BL_RO_DATA_END - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_bl2_setup.c108 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bcm_bl2_plat_arch_setup()
109 BL_RO_DATA_END - BL_RO_DATA_BASE, in bcm_bl2_plat_arch_setup()
H A Dbrcm_bl31_setup.c269 MAP_REGION_FLAT(BL_RO_DATA_BASE, in brcm_bl31_plat_arch_setup()
270 BL_RO_DATA_END - BL_RO_DATA_BASE, in brcm_bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/ti/common/
H A Dti_bl31_setup.c93 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl2_plat_setup.c99 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
100 BL_RO_DATA_END - BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
H A Dbl31_plat_setup.c168 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
169 BL_RO_DATA_END - BL_RO_DATA_BASE, in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/intel/soc/agilex/
H A Dbl2_plat_setup.c104 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
105 BL_RO_DATA_END - BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/plat/intel/soc/n5x/
H A Dbl31_plat_setup.c161 MAP_REGION_FLAT(BL_RO_DATA_BASE, in bl31_plat_arch_setup()
162 BL_RO_DATA_END - BL_RO_DATA_BASE, in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/qti/common/src/
H A Dqti_bl2_setup.c40 BL_RO_DATA_BASE, in bl2_el3_plat_arch_setup()
H A Dqti_bl31_setup.c82 BL_RO_DATA_BASE, in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_bl1_setup.c29 - BL_RO_DATA_BASE, \
H A Dqemu_bl31_setup.c38 BL_RO_DATA_BASE, \
40 - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dbl31_zynqmp_setup.c251 MAP_REGION_FLAT(BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, in bl31_plat_arch_setup()
/rk3399_ARM-atf/plat/arm/board/corstone700/common/include/
H A Dplatform_def.h205 BL_RO_DATA_BASE, \
207 - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/arm/board/fvp_ve/include/
H A Dplatform_def.h110 BL_RO_DATA_BASE, \
112 - BL_RO_DATA_BASE, \
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_bl31_setup.c276 uint64_t rodata_start = BL_RO_DATA_BASE; in bl31_plat_arch_setup()
277 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE; in bl31_plat_arch_setup()

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