| #
1c63cd61 |
| 06-Nov-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentatio
Merge changes from topic "qti-rb3gen2" into integration
* changes:
docs(maintainers): update QTI platform maintainers
docs(qti): add RB3Gen2 platform documentation
docs(qti): move documentation under docs/plat/qti/
feat(kodiak): add support for RB3Gen2 platform
feat(qti): introduce basic XPU driver
refactor(qti): introduce SoC codename as Kodiak
feat(qti): add TF-A BL2 common platform framework
refactor(qti): refactor RNG as a proper driver
fix(qti): fix config PLAT_XLAT_TABLES_DYNAMIC
feat(qti): add BL32 support
refactor(qti): make UART config independent
refactor(qti): make CNTFRQ config independent
fix(qti): fix build without coreboot
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|
| #
292ffc06 |
| 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
feat(qti): introduce basic XPU driver
Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.
Change-Id: I2b5ad50c
feat(qti): introduce basic XPU driver
Introduce basic XPU access control driver which allows currently to
bypass XPU access control until a proper XPU driver is added upstream.
Change-Id: I2b5ad50c57b0112302d3568e0e0bcf2116d3e259
Co-developed-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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|
| #
48897bad |
| 25-Sep-2025 |
Casey Connolly <casey.connolly@linaro.org> |
feat(qti): add BL32 support
Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.
Change-Id: I8ba25f83c
feat(qti): add BL32 support
Add support for loading a BL32 image like OP-TEE. In this case we stop
routing secure EL3 interrupts to EL3 and instead allow S-EL1 to handle
them.
Change-Id: I8ba25f83cfc8749974fb5760392a8c64b2cec18b
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
show more ...
|
| #
8eb87556 |
| 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
refactor(qti): make UART config independent
Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope t
refactor(qti): make UART config independent
Make UART configuration independent of coreboot since there are
alternative bootloaders like TF-A BL2 which can be supported. Also,
configure UART scope to enable runtime logging as well.
Change-Id: I1956535c769c2c3141854d062dc02c289b86b48d
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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|
| #
327a32d9 |
| 25-Sep-2025 |
Sumit Garg <sumit.garg@oss.qualcomm.com> |
refactor(qti): make CNTFRQ config independent
Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.
refactor(qti): make CNTFRQ config independent
Make system counter frequency configuration independent of prior stage
boot-loader like coreboot to enable an alternative boot-loaders such as
TF-A BL2.
Change-Id: Id22803557466643f6455a243929626f71a4714fc
Signed-off-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
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| #
4bd8c929 |
| 09-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I1bfa797e,I0ec7a70e into integration
* changes:
fix(tree): correct some typos
fix(rockchip): use semicolon instead of comma
|
| #
1b491eea |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
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| #
17e76b5e |
| 02-Aug-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "feat(plat/qti): fix to support cpu errata" into integration
|
| #
6cc743cf |
| 04-Apr-2022 |
Saurabh Gorecha <quic_sgorecha@quicinc.com> |
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf1416
feat(plat/qti): fix to support cpu errata
fix to support ARM CPU errata based on core used.
Signed-off-by: Saurabh Gorecha <quic_sgorecha@quicinc.com>
Change-Id: If1a438f98f743435a7a0b683a32ccf14164db37e
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| #
37a12f04 |
| 10-Aug-2020 |
Julius Werner <jwerner@chromium.org> |
Merge "sc7180 platform support" into integration
|
| #
5bd9c17d |
| 22-Apr-2020 |
Saurabh Gorecha <sgorecha@codeaurora.org> |
sc7180 platform support
Adding support for QTI CHIP SC7180 on ATF
Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Mauli
sc7180 platform support
Adding support for QTI CHIP SC7180 on ATF
Change-Id: I0d82d3a378036003fbd0bc4784f61464bb76ea82
Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
Co-authored-by: Maulik Shah <mkshah@codeaurora.org>
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|