1 /*
2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9
10 #include <bl31/bl31.h>
11 #include <common/debug.h>
12 #include <common/desc_image_load.h>
13 #include <drivers/console.h>
14 #include <drivers/generic_delay_timer.h>
15 #include <drivers/qti/accesscontrol/xpu.h>
16 #include <lib/bl_aux_params/bl_aux_params.h>
17 #include <lib/coreboot.h>
18 #include <lib/spinlock.h>
19
20 #include <platform.h>
21 #include <qti_interrupt_svc.h>
22 #include <qti_plat.h>
23 #include <qti_uart_console.h>
24 #include <qtiseclib_interface.h>
25
26 /* Variable to hold QTI UART configuration */
27 static console_t g_qti_console_uart;
28
29 /*
30 * Placeholder variables for copying the BL32 and Bl33 arguments that have been
31 * passed to BL31 from BL2.
32 */
33 static entry_point_info_t bl32_image_ep_info;
34 static entry_point_info_t bl33_image_ep_info;
35
36 /*
37 * Variable to hold bl31 cold boot status. Default value 0x0 means yet to boot.
38 * Any other value means cold booted.
39 */
40 uint32_t g_qti_bl31_cold_booted;
41
42 /*******************************************************************************
43 * Perform any BL31 early platform setup common to ARM standard platforms.
44 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
45 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be
46 * done before the MMU is initialized so that the memory layout can be used
47 * while creating page tables. BL2 has flushed this information to memory, so
48 * we are guaranteed to pick up good data.
49 ******************************************************************************/
bl31_early_platform_setup(u_register_t from_bl2,u_register_t plat_params_from_bl2)50 void bl31_early_platform_setup(u_register_t from_bl2,
51 u_register_t plat_params_from_bl2)
52 {
53 bl_aux_params_parse(plat_params_from_bl2, NULL);
54
55 qti_console_uart_register(&g_qti_console_uart, PLAT_QTI_UART_BASE);
56 console_set_scope(&g_qti_console_uart, CONSOLE_FLAG_RUNTIME |
57 CONSOLE_FLAG_BOOT | CONSOLE_FLAG_CRASH);
58 /*
59 * Tell BL31 where the non-trusted software image
60 * is located and the entry state information
61 */
62 bl31_params_parse_helper(from_bl2, &bl32_image_ep_info, &bl33_image_ep_info);
63 }
64
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)65 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
66 u_register_t arg2, u_register_t arg3)
67 {
68 bl31_early_platform_setup(arg0, arg1);
69 }
70
71 /*******************************************************************************
72 * Perform the very early platform specific architectural setup here. At the
73 * moment this only initializes the mmu in a quick and dirty way.
74 ******************************************************************************/
bl31_plat_arch_setup(void)75 void bl31_plat_arch_setup(void)
76 {
77 qti_setup_page_tables(
78 BL31_START,
79 BL31_END-BL31_START,
80 BL_CODE_BASE,
81 BL_CODE_END,
82 BL_RO_DATA_BASE,
83 BL_RO_DATA_END
84 );
85 enable_mmu_el3(0);
86 }
87
88 /*******************************************************************************
89 * Perform any BL31 platform setup common to ARM standard platforms
90 ******************************************************************************/
bl31_platform_setup(void)91 void bl31_platform_setup(void)
92 {
93 #ifdef QTI_MSM_XPU_BYPASS
94 INFO("Bypassing QTI MSM XPU...\n");
95 qti_msm_xpu_bypass();
96 #endif
97 generic_delay_timer_init();
98 /* Initialize the GIC driver, CPU and distributor interfaces */
99 plat_qti_gic_driver_init();
100 plat_qti_gic_init();
101 qti_interrupt_svc_init(bl32_image_ep_info.pc != 0);
102 qtiseclib_bl31_platform_setup();
103
104 /* set boot state to cold boot complete. */
105 g_qti_bl31_cold_booted = 0x1;
106 }
107
108 /*******************************************************************************
109 * Return a pointer to the 'entry_point_info' structure of the next image for the
110 * security state specified. BL33 corresponds to the non-secure image type
111 * while BL32 corresponds to the secure image type. A NULL pointer is returned
112 * if the image does not exist.
113 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)114 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
115 {
116 entry_point_info_t *ep;
117
118 assert(sec_state_is_valid(type) != 0);
119 ep = (type == SECURE) ? &bl32_image_ep_info : &bl33_image_ep_info;
120
121 return ep->pc ? ep : NULL;
122 }
123
124 /*******************************************************************************
125 * This function is used by the architecture setup code to retrieve the counter
126 * frequency for the CPU's generic timer. This value will be programmed into the
127 * CNTFRQ_EL0 register. In Arm standard platforms, it returns the base frequency
128 * of the system counter, which is retrieved from the first entry in the
129 * frequency modes table. This will be used later in warm boot (psci_arch_setup)
130 * of CPUs to set when CPU frequency.
131 ******************************************************************************/
plat_get_syscnt_freq2(void)132 unsigned int plat_get_syscnt_freq2(void)
133 {
134 return PLAT_SYSCNT_FREQ;
135 }
136