| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_common.c | 162 #ifdef ARM_SYS_CNTCTL_BASE
169 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
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| H A D | arm_bl31_setup.c | 446 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in arm_bl31_platform_setup()
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| /rk3399_ARM-atf/plat/arm/common/sp_min/ |
| H A D | arm_sp_min_setup.c | 260 #ifdef ARM_SYS_CNTCTL_BASE in sp_min_platform_setup()
261 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in sp_min_platform_setup()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/ |
| H A D | bl31_plat_setup.c | 74 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF, reg_cntfid); in bl31_platform_setup()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/aarch64/ |
| H A D | platform_common.c | 91 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/include/ |
| H A D | rcar_def.h | 95 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE macro
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/aarch64/ |
| H A D | platform_common.c | 103 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
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| /rk3399_ARM-atf/plat/arm/board/fvp/ |
| H A D | fvp_bl31_setup.c | 174 counter_base_frequency = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
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| H A D | fvp_common.c | 545 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in fvp_timer_init()
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| /rk3399_ARM-atf/plat/renesas/rcar_gen4/include/ |
| H A D | rcar_def.h | 118 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE macro
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| /rk3399_ARM-atf/plat/renesas/rcar_gen5/ |
| H A D | bl31_plat_setup.c | 162 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl31_platform_setup()
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| /rk3399_ARM-atf/plat/nuvoton/npcm845x/ |
| H A D | npcm845x_bl31_setup.c | 288 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, in bl31_platform_setup()
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| /rk3399_ARM-atf/plat/arm/board/corstone700/common/include/ |
| H A D | platform_def.h | 127 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) macro
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| /rk3399_ARM-atf/include/plat/arm/common/ |
| H A D | arm_def.h | 458 #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE macro
460 #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) macro
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| /rk3399_ARM-atf/plat/arm/board/corstone1000/common/include/ |
| H A D | platform_def.h | 231 #define ARM_SYS_CNTCTL_BASE UL(0x1a200000) macro
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| /rk3399_ARM-atf/plat/renesas/common/aarch64/ |
| H A D | platform_common.c | 213 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
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| /rk3399_ARM-atf/plat/arm/board/tc/include/ |
| H A D | platform_def.h | 21 #ifdef ARM_SYS_CNTCTL_BASE
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| /rk3399_ARM-atf/plat/renesas/common/include/ |
| H A D | rcar_def.h | 206 #define ARM_SYS_CNTCTL_BASE RCAR_CNTC_BASE macro
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| /rk3399_ARM-atf/include/plat/nuvoton/common/ |
| H A D | npcm845x_arm_def.h | 370 #define ARM_SYS_CNTCTL_BASE UL(0XF07FC000) macro
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/include/nrd3/ |
| H A D | nrd_plat_arm_def3.h | 150 #define ARM_SYS_CNTCTL_BASE NRD_CSS_GENERIC_REFCLK_BASE macro
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| /rk3399_ARM-atf/plat/renesas/rzg/ |
| H A D | bl2_plat_setup.c | 1016 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()
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| /rk3399_ARM-atf/plat/renesas/rcar/ |
| H A D | bl2_plat_setup.c | 1414 mmio_write_32(ARM_SYS_CNTCTL_BASE + (uintptr_t)CNTFID_OFF, reg_cntfid); in bl2_init_generic_timer()
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