| #
2b6ae948 |
| 23-Sep-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "refactor(tc): neaten platform code after TC2 removal" into integration
|
| #
8de6021b |
| 22-Sep-2025 |
Ryan Everett <ryan.everett@arm.com> |
refactor(tc): neaten platform code after TC2 removal
Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dts
refactor(tc): neaten platform code after TC2 removal
Now that TC2 has been removed, the only TC platforms
are TC3 and TC4. Therefore, it no longer makes sense
to have both tc-base and tc3-4-base dtsi files.
This patch combines the two base TC dtsi files,
and removes tautological ifdefs in TC platform code.
Change-Id: I011b5fe1f645d6d53276007b11a17bd6cf952ecb
Signed-off-by: Ryan Everett <ryan.everett@arm.com>
show more ...
|
| #
cb68fefb |
| 31-Jul-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mv_ns_buf_to_ns_dram" into integration
* changes:
feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE
feat(fvp): add extra DRAM configuration for TZC
feat(fvp): change PLAT_
Merge changes from topic "mv_ns_buf_to_ns_dram" into integration
* changes:
feat(juno): change PLAT_SP_IMAGE_NS_BUF_BASE
feat(fvp): add extra DRAM configuration for TZC
feat(fvp): change PLAT_SP_IMAGE_NS_BUF_BASE
feat(neoverse-rd): change PLAT_SP_IMAGE_NS_BUF_BASE
feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE
feat(arm): introduce ARM_SPM_NS_MEM_BASE and move NS buffer
show more ...
|
| #
22e97b78 |
| 07-Jul-2025 |
Yeoreum Yun <yeoreum.yun@arm.com> |
feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE
As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
Link
feat(tc): change PLAT_SP_IMAGE_NS_BUF_BASE
As PLAT_SP_IMAGE_NS_BUF_BASE is moved to NS_DRAM1 area [0],
PLAT_ARM_SP_IMAGE_STACK_BASE should be changed to
(PLAT_SPM_BUF_BASE + PLAT_SPM_BUF_SIZE)
Link: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/40336 [0]
Signed-off-by: Yeoreum Yun <yeoreum.yun@arm.com>
Change-Id: I6e97954a1ce91fdbda4edcdba5ccfa1d7c8ff475
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|
| #
c76da4ec |
| 25-Apr-2025 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "chore(tc): remove TC2 platform variant" into integration
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| #
f036ddaf |
| 09-Apr-2025 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
chore(tc): remove TC2 platform variant
Remove TC2 platform support which was deprecated in the last release.
Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <M
chore(tc): remove TC2 platform variant
Remove TC2 platform support which was deprecated in the last release.
Change-Id: Ibf4a94a0168151ebc66eaca044a143c51e974a1f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
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| #
29de2aa4 |
| 03-Apr-2025 |
Govindraj Raja <govindraj.raja@arm.com> |
Merge changes from topic "jc/tc_fw_handoff" into integration
* changes:
feat(tc): port BL31-BL33 interface to firmware handoff framework
feat(tc): port BL2-BL31 interface to firmware handoff fra
Merge changes from topic "jc/tc_fw_handoff" into integration
* changes:
feat(tc): port BL31-BL33 interface to firmware handoff framework
feat(tc): port BL2-BL31 interface to firmware handoff framework
feat(tc): port BL1-BL2 interface to firmware handoff framework
show more ...
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| #
25a6bcd5 |
| 01-Mar-2025 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(tc): port BL31-BL33 interface to firmware handoff framework
Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.
Signed-off-by: Jayanth Dodderi
feat(tc): port BL31-BL33 interface to firmware handoff framework
Adding support for this framework at the handoff boundary between
firmware stage BL31 and BL33 on TC.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Ia6cd29c8b6cdda0a127a3bac02f6fa1dcfc07151
show more ...
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| #
93c50ae6 |
| 01-Mar-2025 |
Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> |
feat(tc): port BL1-BL2 interface to firmware handoff framework
The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this
feat(tc): port BL1-BL2 interface to firmware handoff framework
The firmware handoff framework, is a light weight mechanism for
sharing information between bootloader stages.
Adding support for this framework at the handoff boundary between
firmware stage BL1 and BL2 on TC.
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
Change-Id: Iae13adbcdd6ebbdcc61d04e017655c6b8d715ea0
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| #
bf6b1513 |
| 23-Jan-2025 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration
* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FP
Merge changes I70b68b06,I7b180c3e,Id4ad925d,Ie31933e0,Ie8fe1f1d, ... into integration
* changes:
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
fix(tc): modify ethernet configuration for TC4 FPGA
fix(tc): modify gpio controller base addr for TC4 FPGA
fix(tc): modify DPU configuration in dts for TC4 FPGA
fix(tc): modify mmc configuration for TC4 FPGA
feat(tc): configure UART for TC4 FPGA
show more ...
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| #
bea55e3c |
| 15-Aug-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.
Change-Id: I70b68b06501d17dcebbe78bee8fec0a70
refactor(tc): rename TC_FPGA_ANDROID_IMG_IN_RAM
Rename TC_FPGA_ANDROID_IMG_IN_RAM to TC_FPGA_FS_IMG_IN_RAM
to use it for debian loading to ram as well.
Change-Id: I70b68b06501d17dcebbe78bee8fec0a701106c92
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
84ca47a8 |
| 28-Jun-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
feat(tc): configure UART for TC4 FPGA
TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.
Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Ge
feat(tc): configure UART for TC4 FPGA
TC4 FPGA have a UART clock of 4000000 so modify the value
of TC_UARTCLK for TC4.
Change-Id: I8de84d58bce8b7277bf356136a5185c008ab4c28
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
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| #
78f9c437 |
| 08-Jan-2025 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I58ba6b70,Id463a9dd into integration
* changes:
fix(tc): set console baurate to 38400 for fvp as well
refactor(tc): remove redundant macro UARTCLK_FREQ
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| #
54289385 |
| 13-Aug-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
fix(tc): set console baurate to 38400 for fvp as well
Set console baurate to 38400 for fvp as well for code
simplicity.
Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish G
fix(tc): set console baurate to 38400 for fvp as well
Set console baurate to 38400 for fvp as well for code
simplicity.
Change-Id: I58ba6b7043541f6eb67e32257307da4eba0bb28a
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
25264e29 |
| 28-Jun-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
refactor(tc): remove redundant macro UARTCLK_FREQ
remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.
Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagd
refactor(tc): remove redundant macro UARTCLK_FREQ
remove redundant macro UARTCLK_FREQ and replace it with TC_UARTCLK
in dts.
Change-Id: Id463a9ddc1588278e552ffca3dfb738676229ce7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen.Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
8a7a54b4 |
| 19-Dec-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "mcn" into integration
* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure acc
Merge changes from topic "mcn" into integration
* changes:
feat(tc): add MCN PMU nodes in dts for TC4
feat(tc): add 'kaslr-seed' node in device tree for TC3
feat(tc): enable MCN non-secure access to pmu counters on TC4
feat(tc): define MCN related macros for TC4
show more ...
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| #
8f61c204 |
| 19-Jun-2024 |
Jagdish Gediya <jagdish.gediya@arm.com> |
feat(tc): define MCN related macros for TC4
Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.
Signed-off-by: Jagdish Ged
feat(tc): define MCN related macros for TC4
Define MCN related macros for TC4 to add TC4 specific MCN PMU
nodes in dts and to enable MCN PMU NS access in further commits.
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ifc02fcd833888a9953fac404585468316aa0168c
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| #
15e5c6c9 |
| 05-Dec-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes I00d2de7b,I5ec82646 into integration
* changes:
feat(tc): fpga: Enable support for loading FIP image to DRAM
feat(tc): allow Android load and Boot From RAM
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| #
969b7591 |
| 23-Apr-2024 |
Vishnu Satheesh <vishnu.satheesh@arm.com> |
feat(tc): fpga: Enable support for loading FIP image to DRAM
This patch enable support for loading FIP image into DRAM rather than
flash drive.
Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
feat(tc): fpga: Enable support for loading FIP image to DRAM
This patch enable support for loading FIP image into DRAM rather than
flash drive.
Change-Id: I00d2de7b22e315db7f3e8a835ddd414ab297b554
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
932e64a1 |
| 23-Apr-2024 |
Vishnu Satheesh <vishnu.satheesh@arm.com> |
feat(tc): allow Android load and Boot From RAM
This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loadi
feat(tc): allow Android load and Boot From RAM
This commit introduces the below changes:
* Define TC_FPGA_ANDROID_IMG_IN_RAM config variable
* Add phram node in dts.
* Memory configuration for loading Android image
Change-Id: I5ec82646cb2993e7b5976e702ebcc8efa51d1128
Signed-off-by: Vishnu Satheesh <vishnu.satheesh@arm.com>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
1286de42 |
| 05-Dec-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default" into integration
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| #
d8eaa0c3 |
| 05-Dec-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(tc): increase SCP BL2 size to support optimization 0" into integration
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| #
3755e82c |
| 10-May-2024 |
Tintu Thomas <tintu.thomas@arm.com> |
feat(tc): increase SCP BL2 size to support optimization 0
It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.
Signed-o
feat(tc): increase SCP BL2 size to support optimization 0
It requires at least 140 KB to support SCP BL2 optimization 0.
Increase the size to 192 KB (0x30000) considering space for growth.
Signed-off-by: Tintu Thomas <tintu.thomas@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Change-Id: Ib416c89226475d44746a7561dd949a14349c3e4b
show more ...
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| #
cab72858 |
| 10-Oct-2024 |
Ben Horgan <ben.horgan@arm.com> |
chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default
Previously we only enabled 8GB unless we were loading the filesystem
from RAM.
Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
S
chore(tc): enable the full 16GB DRAM for TC3 and TC4 as default
Previously we only enabled 8GB unless we were loading the filesystem
from RAM.
Change-Id: Iae60ef460b8cf70f28e62a79db32405daf029e8a
Signed-off-by: Ben Horgan <ben.horgan@arm.com>
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
show more ...
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| #
a8c21f17 |
| 24-Oct-2024 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(tc): retain NS timer frame ID for TC2 as 0" into integration
|