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Searched refs:base (Results 1 – 25 of 225) sorted by relevance

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/optee_os/core/drivers/
H A Dtzc400.c73 vaddr_t base; member
82 static uint32_t tzc_read_build_config(vaddr_t base) in tzc_read_build_config() argument
84 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
87 static uint32_t tzc_read_gate_keeper(vaddr_t base) in tzc_read_gate_keeper() argument
89 return io_read32(base + GATE_KEEPER_OFF); in tzc_read_gate_keeper()
92 static void tzc_write_gate_keeper(vaddr_t base, uint32_t val) in tzc_write_gate_keeper() argument
94 io_write32(base + GATE_KEEPER_OFF, val); in tzc_write_gate_keeper()
97 static void tzc_write_action(vaddr_t base, enum tzc_action action) in tzc_write_action() argument
99 io_write32(base + ACTION_OFF, action); in tzc_write_action()
102 static uint32_t tzc_read_region_base_low(vaddr_t base, uint32_t region) in tzc_read_region_base_low() argument
[all …]
H A Dtzc380.c48 vaddr_t base; member
55 static uint32_t tzc_read_build_config(vaddr_t base) in tzc_read_build_config() argument
57 return io_read32(base + BUILD_CONFIG_OFF); in tzc_read_build_config()
60 static void tzc_write_action(vaddr_t base, enum tzc_action action) in tzc_write_action() argument
62 io_write32(base + ACTION_OFF, action); in tzc_write_action()
65 static uint32_t tzc_read_action(vaddr_t base) in tzc_read_action() argument
67 return io_read32(base + ACTION_OFF); in tzc_read_action()
70 static void tzc_write_region_base_low(vaddr_t base, uint32_t region, in tzc_write_region_base_low() argument
73 io_write32(base + REGION_SETUP_LOW_OFF(region), val); in tzc_write_region_base_low()
76 static void tzc_write_region_base_high(vaddr_t base, uint32_t region, in tzc_write_region_base_high() argument
[all …]
H A Dhi16xx_uart.c66 return io_pa_or_va(&pd->base, HI16XX_UART_REG_SIZE); in chip_to_base()
71 vaddr_t base = chip_to_base(chip); in hi16xx_uart_flush() local
73 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_flush()
79 vaddr_t base = chip_to_base(chip); in hi16xx_uart_putc() local
82 while (!(io_read32(base + UART_USR) & UART_USR_TFE_BIT)) in hi16xx_uart_putc()
86 io_write32(base + UART_THR, ch & 0xFF); in hi16xx_uart_putc()
91 vaddr_t base = chip_to_base(chip); in hi16xx_uart_have_rx_data() local
93 return (io_read32(base + UART_USR) & UART_USR_RFNE_BIT); in hi16xx_uart_have_rx_data()
98 vaddr_t base = chip_to_base(chip); in hi16xx_uart_getchar() local
102 return io_read32(base + UART_RBR) & 0xFF; in hi16xx_uart_getchar()
[all …]
H A Dmvebu_uart.c62 return io_pa_or_va(&pd->base, UART_SIZE); in chip_to_base()
67 vaddr_t base = chip_to_base(chip); in mvebu_uart_flush() local
76 while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY)) in mvebu_uart_flush()
82 vaddr_t base = chip_to_base(chip); in mvebu_uart_have_rx_data() local
84 return (io_read32(base + UART_STATUS_REG) & UART_RX_READY); in mvebu_uart_have_rx_data()
89 vaddr_t base = chip_to_base(chip); in mvebu_uart_getchar() local
93 return io_read32(base + UART_RX_REG) & 0xff; in mvebu_uart_getchar()
98 vaddr_t base = chip_to_base(chip); in mvebu_uart_putc() local
103 tmp = io_read32(base + UART_STATUS_REG); in mvebu_uart_putc()
107 io_write32(base + UART_TX_REG, ch); in mvebu_uart_putc()
[all …]
H A Dsifive_uart.c30 return io_pa_or_va(&pd->base, SIFIVE_UART_REG_SIZE); in chip_to_base()
35 vaddr_t base = chip_to_base(chip); in sifive_uart_flush() local
37 while (io_read32(base + UART_REG_TXFIFO) & UART_TXFIFO_FULL) { in sifive_uart_flush()
45 vaddr_t base = chip_to_base(chip); in sifive_uart_have_rx_data() local
47 return !(io_read32(base + UART_REG_RXFIFO) & UART_RXFIFO_EMPTY); in sifive_uart_have_rx_data()
52 vaddr_t base = chip_to_base(chip); in sifive_uart_getchar() local
58 return io_read32(base + UART_REG_RXFIFO) & UART_RXFIFO_DATA; in sifive_uart_getchar()
63 vaddr_t base = chip_to_base(chip); in sifive_uart_putc() local
68 io_write32(base + UART_REG_TXFIFO, ch); in sifive_uart_putc()
78 void sifive_uart_init(struct sifive_uart_data *pd, paddr_t base, in sifive_uart_init() argument
[all …]
H A Dpl011.c85 return io_pa_or_va(&pd->base, PL011_REG_SIZE); in chip_to_base()
90 vaddr_t base = chip_to_base(chip); in pl011_flush() local
99 while ((io_read32(base + UART_CR) & UART_CR_UARTEN) && in pl011_flush()
100 !(io_read32(base + UART_FR) & UART_FR_TXFE)) in pl011_flush()
106 vaddr_t base = chip_to_base(chip); in pl011_have_rx_data() local
108 return !(io_read32(base + UART_FR) & UART_FR_RXFE); in pl011_have_rx_data()
113 vaddr_t base = chip_to_base(chip); in pl011_getchar() local
117 return io_read32(base + UART_DR) & 0xff; in pl011_getchar()
122 vaddr_t base = chip_to_base(chip); in pl011_putc() local
125 while (io_read32(base + UART_FR) & UART_FR_TXFF) in pl011_putc()
[all …]
H A Datmel_uart.c58 return io_pa_or_va(&pd->base, ATMEL_UART_SIZE); in chip_to_base()
63 vaddr_t base = chip_to_base(chip); in atmel_uart_flush() local
65 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXEMPTY)) in atmel_uart_flush()
71 vaddr_t base = chip_to_base(chip); in atmel_uart_getchar() local
73 while (io_read32(base + ATMEL_UART_SR) & ATMEL_SR_RXRDY) in atmel_uart_getchar()
76 return io_read32(base + ATMEL_UART_RHR); in atmel_uart_getchar()
81 vaddr_t base = chip_to_base(chip); in atmel_uart_putc() local
83 while (!(io_read32(base + ATMEL_UART_SR) & ATMEL_SR_TXRDY)) in atmel_uart_putc()
86 io_write32(base + ATMEL_UART_THR, ch); in atmel_uart_putc()
95 void atmel_uart_init(struct atmel_uart_data *pd, paddr_t base) in atmel_uart_init() argument
[all …]
H A Damlogic_uart.c30 return io_pa_or_va(&pd->base, AML_UART_SIZE); in chip_to_base()
35 vaddr_t base = chip_to_base(chip); in amlogic_uart_flush() local
37 while (!(io_read32(base + AML_UART_STATUS) & AML_UART_TX_EMPTY)) in amlogic_uart_flush()
43 vaddr_t base = chip_to_base(chip); in amlogic_uart_getchar() local
45 if (io_read32(base + AML_UART_STATUS) & AML_UART_RX_EMPTY) in amlogic_uart_getchar()
48 return io_read32(base + AML_UART_RFIFO) & 0xff; in amlogic_uart_getchar()
53 vaddr_t base = chip_to_base(chip); in amlogic_uart_putc() local
55 while (io_read32(base + AML_UART_STATUS) & AML_UART_TX_FULL) in amlogic_uart_putc()
58 io_write32(base + AML_UART_WFIFO, ch); in amlogic_uart_putc()
67 void amlogic_uart_init(struct amlogic_uart_data *pd, paddr_t base) in amlogic_uart_init() argument
[all …]
H A Dscif.c53 return io_pa_or_va(&pd->base, SCIF_REG_SIZE); in chip_to_base()
58 vaddr_t base = chip_to_base(chip); in scif_uart_flush() local
60 while (!(io_read16(base + SCIF_SCFSR) & SCFSR_TEND)) in scif_uart_flush()
66 vaddr_t base = chip_to_base(chip); in scif_uart_putc() local
69 while ((io_read16(base + SCIF_SCFDR) >> SCFDR_T_SHIFT) >= in scif_uart_putc()
72 io_write8(base + SCIF_SCFTDR, ch); in scif_uart_putc()
73 io_clrbits16(base + SCIF_SCFSR, SCFSR_TEND | SCFSR_TDFE); in scif_uart_putc()
84 vaddr_t base; in scif_uart_init() local
86 pd->base.pa = pbase; in scif_uart_init()
89 base = io_pa_or_va(&pd->base, SCIF_REG_SIZE); in scif_uart_init()
[all …]
H A Dsprd_uart.c49 return io_pa_or_va(&pd->base, UART_SIZE); in chip_to_base()
54 vaddr_t base = chip_to_base(chip); in sprd_uart_flush() local
56 while (io_read32(base + UART_STS1) & STS1_TXF_CNT_MASK) in sprd_uart_flush()
62 vaddr_t base = chip_to_base(chip); in sprd_uart_have_rx_data() local
64 return !!(io_read32(base + UART_STS1) & STS1_RXF_CNT_MASK); in sprd_uart_have_rx_data()
69 vaddr_t base = chip_to_base(chip); in sprd_uart_putc() local
72 io_write32(base + UART_TXD, ch); in sprd_uart_putc()
77 vaddr_t base = chip_to_base(chip); in sprd_uart_getchar() local
82 return io_read32(base + UART_RXD) & 0xff; in sprd_uart_getchar()
93 void sprd_uart_init(struct sprd_uart_data *pd, paddr_t base) in sprd_uart_init() argument
[all …]
H A Dcdns_uart.c64 return io_pa_or_va(&pd->base, CDNS_UART_SIZE); in chip_to_base()
69 vaddr_t base = chip_to_base(chip); in cdns_uart_flush() local
71 while (!(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_flush()
78 vaddr_t base = chip_to_base(chip); in cdns_uart_have_rx_data() local
80 return !(io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_have_rx_data()
86 vaddr_t base = chip_to_base(chip); in cdns_uart_getchar() local
90 return io_read32(base + CDNS_UART_FIFO) & 0xff; in cdns_uart_getchar()
95 vaddr_t base = chip_to_base(chip); in cdns_uart_putc() local
98 while (io_read32(base + CDNS_UART_CHANNEL_STATUS) & in cdns_uart_putc()
103 io_write32(base + CDNS_UART_FIFO, ch); in cdns_uart_putc()
[all …]
H A Drockchip_otp.c46 vaddr_t base = (vaddr_t)phys_to_virt(OTP_S_BASE, MEM_AREA_IO_SEC, in rockchip_otp_read_secure() local
54 if (!base) in rockchip_otp_read_secure()
68 io_write32(base + OTP_S_INT_ST, io_read32(base + OTP_S_INT_ST)); in rockchip_otp_read_secure()
71 io_write32(base + OTP_S_AUTO_CTRL, auto_ctrl_val); in rockchip_otp_read_secure()
74 io_write32(base + OTP_S_AUTO_EN, EN_ENABLE); in rockchip_otp_read_secure()
77 res = IO_READ32_POLL_TIMEOUT(base + OTP_S_INT_ST, in rockchip_otp_read_secure()
85 io_write32(base + OTP_S_INT_ST, io_read32(base + OTP_S_INT_ST)); in rockchip_otp_read_secure()
98 val = io_read32(base + OTP_S_DOUT + in rockchip_otp_read_secure()
109 vaddr_t base = (vaddr_t)phys_to_virt(OTP_S_BASE, MEM_AREA_IO_SEC, in rockchip_otp_write_secure() local
114 if (!base) in rockchip_otp_write_secure()
[all …]
H A Dimx_snvs.c70 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_otpmk_selected() local
72 hp_mks = io_read32(base + SNVS_HPCOMR); in is_otpmk_selected()
79 uint32_t lp_mks = io_read32(base + SNVS_LPMKCR); in is_otpmk_selected()
93 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in is_mks_locked() local
95 return io_read32(base + SNVS_HPLR) & SNVS_HPLR_MKS_SL || in is_mks_locked()
96 io_read32(base + SNVS_LPLR) & SNVS_LPLR_MKS_HL; in is_mks_locked()
102 vaddr_t base = core_mmu_get_va(SNVS_BASE, MEM_AREA_IO_SEC, SNVS_SIZE); in set_mks_otpmk() local
104 io_setbits32(base + SNVS_HPCOMR, SNVS_HPCOMR_MKS_EN); in set_mks_otpmk()
105 io_clrbits32(base + SNVS_LPMKCR, SNVS_LPMKCR_MKCR_MKS_SEL); in set_mks_otpmk()
106 io_clrbits32(base + SNVS_HPLR, SNVS_HPLR_MKS_SL); in set_mks_otpmk()
[all …]
H A Dqcom_geni_uart.c25 vaddr_t base = io_pa_or_va(&pd->base, GENI_UART_REG_SIZE); in qcom_geni_uart_putc() local
28 while (io_read32(base + GENI_STATUS_REG) & GENI_STATUS_REG_CMD_ACTIVE) in qcom_geni_uart_putc()
32 io_write32(base + GENI_TX_TRANS_LEN_REG, 1); in qcom_geni_uart_putc()
33 io_write32(base + GENI_M_CMD0_REG, GENI_M_CMD_TX); in qcom_geni_uart_putc()
34 io_write32(base + GENI_TX_FIFO_REG, ch); in qcom_geni_uart_putc()
42 void qcom_geni_uart_init(struct qcom_geni_uart_data *pd, paddr_t base) in qcom_geni_uart_init() argument
44 pd->base.pa = base; in qcom_geni_uart_init()
H A Dstm32_uart.c55 return io_pa_or_va(&pd->base, 1); in loc_chip_to_base()
60 vaddr_t base = loc_chip_to_base(chip); in loc_flush() local
63 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXFE)) in loc_flush()
70 vaddr_t base = loc_chip_to_base(chip); in loc_putc() local
73 while (!(io_read32(base + UART_REG_ISR) & USART_ISR_TXE_TXFNF)) in loc_putc()
77 io_write32(base + UART_REG_TDR, ch); in loc_putc()
82 vaddr_t base = loc_chip_to_base(chip); in loc_have_rx_data() local
84 return io_read32(base + UART_REG_ISR) & USART_ISR_RXNE_RXFNE; in loc_have_rx_data()
89 vaddr_t base = loc_chip_to_base(chip); in loc_getchar() local
94 return io_read32(base + UART_REG_RDR) & 0xff; in loc_getchar()
[all …]
H A Dsp805_wdt.c20 return io_pa_or_va(&pd->base, WDT_SIZE); in chip_to_base()
50 vaddr_t base = chip_to_base(chip); in sp805_config() local
52 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_config()
53 io_write32(base + WDT_LOAD_OFFSET, pd->load_val); in sp805_config()
54 io_write32(base + WDT_INTCLR_OFFSET, WDT_INT_CLR); in sp805_config()
57 io_write32(base + WDT_CONTROL_OFFSET, in sp805_config()
60 io_write32(base + WDT_LOCK_OFFSET, WDT_LOCK_KEY); in sp805_config()
63 (void)io_read32(base + WDT_LOCK_OFFSET); in sp805_config()
78 vaddr_t base = chip_to_base(chip); in sp805_disable() local
80 io_write32(base + WDT_LOCK_OFFSET, WDT_UNLOCK_KEY); in sp805_disable()
[all …]
H A Dstih_asc.c22 return io_pa_or_va(&pd->base, STIH_ASC_REG_SIZE); in chip_to_base()
27 vaddr_t base = chip_to_base(chip); in stih_asc_flush() local
29 while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_EMPTY)) in stih_asc_flush()
35 vaddr_t base = chip_to_base(chip); in stih_asc_putc() local
37 while (!(io_read32(base + ASC_STATUS) & ASC_STATUS_TX_HALF_EMPTY)) in stih_asc_putc()
40 io_write32(base + ASC_TXBUFFER, ch); in stih_asc_putc()
49 void stih_asc_init(struct stih_asc_pd *pd, vaddr_t base) in stih_asc_init() argument
51 pd->base.pa = base; in stih_asc_init()
H A Dns16550.c54 return io_pa_or_va(&(*pd)->base, NS16550_UART_REG_SIZE); in chip_to_base_and_data()
60 vaddr_t base = chip_to_base_and_data(chip, &pd); in ns16550_flush() local
62 while ((serial_in(base + (UART_LSR << pd->reg_shift), pd->io_width) & in ns16550_flush()
70 vaddr_t base = chip_to_base_and_data(chip, &pd); in ns16550_putc() local
75 serial_out(base + (UART_THR << pd->reg_shift), pd->io_width, ch); in ns16550_putc()
81 vaddr_t base = chip_to_base_and_data(chip, &pd); in ns16550_have_rx_data() local
83 return serial_in(base + (UART_LSR << pd->reg_shift), pd->io_width) & in ns16550_have_rx_data()
90 vaddr_t base = chip_to_base_and_data(chip, &pd); in ns16550_getchar() local
97 return serial_in(base + (UART_RBR << pd->reg_shift), pd->io_width) & in ns16550_getchar()
109 void ns16550_init(struct ns16550_data *pd, paddr_t base, uint8_t io_width, in ns16550_init() argument
[all …]
/optee_os/core/arch/arm/plat-bcm/
H A Dbcm_elog.c15 vaddr_t base = 0; in bcm_elog_putchar() local
17 base = io_pa_or_va(&elog->base, elog->max_size); in bcm_elog_putchar()
19 offset = io_read32(base + BCM_ELOG_OFF_OFFSET); in bcm_elog_putchar()
20 len = io_read32(base + BCM_ELOG_LEN_OFFSET); in bcm_elog_putchar()
21 io_write8(base + offset, ch); in bcm_elog_putchar()
32 io_write32(base + BCM_ELOG_OFF_OFFSET, offset); in bcm_elog_putchar()
33 io_write32(base + BCM_ELOG_LEN_OFFSET, len); in bcm_elog_putchar()
40 vaddr_t base = 0; in bcm_elog_init() local
42 elog->base.pa = pa_base; in bcm_elog_init()
45 base = io_pa_or_va(&elog->base, BCM_ELOG_HEADER_LEN); in bcm_elog_init()
[all …]
/optee_os/lib/libutils/isoc/newlib/
H A Dstrtoul.c158 _DEFUN (_strtoul, (nptr, endptr, base),
161 int base)
180 if ((base == 0 || base == 16) &&
184 base = 16;
186 if (base == 0)
187 base = c == '0' ? 8 : 10;
188 cutoff = (unsigned long)ULONG_MAX / (unsigned long)base;
189 cutlim = (unsigned long)ULONG_MAX % (unsigned long)base;
197 if (c >= base)
203 acc *= base;
[all …]
/optee_os/core/drivers/imx/mu/
H A Dimx_mu_8ulp_9x.c43 unsigned int imx_mu_plat_get_rx_channel(vaddr_t base) in imx_mu_plat_get_rx_channel() argument
45 return (io_read32(base + MU_PAR) & RR_NUM_MASK) >> RR_NUM_SHIFT; in imx_mu_plat_get_rx_channel()
48 unsigned int imx_mu_plat_get_tx_channel(vaddr_t base) in imx_mu_plat_get_tx_channel() argument
50 return io_read32(base + MU_PAR) & TR_NUM_MASK; in imx_mu_plat_get_tx_channel()
53 TEE_Result imx_mu_plat_send(vaddr_t base, unsigned int index, uint32_t msg) in imx_mu_plat_send() argument
55 assert(index < imx_mu_plat_get_tx_channel(base)); in imx_mu_plat_send()
58 if (mu_wait_for(base + MU_TSR, MU_TSR_TE(index))) in imx_mu_plat_send()
61 io_write32(base + MU_TR(index), msg); in imx_mu_plat_send()
66 TEE_Result imx_mu_plat_receive(vaddr_t base, unsigned int index, uint32_t *msg) in imx_mu_plat_receive() argument
68 assert(index < imx_mu_plat_get_rx_channel(base)); in imx_mu_plat_receive()
[all …]
H A Dimx_mu.c25 __weak void imx_mu_plat_init(vaddr_t base __unused) in imx_mu_plat_init()
29 __weak TEE_Result imx_mu_plat_send(vaddr_t base __unused, in imx_mu_plat_send()
36 __weak TEE_Result imx_mu_plat_receive(vaddr_t base __unused, in imx_mu_plat_receive()
49 static TEE_Result imx_mu_receive_msg(vaddr_t base, struct imx_mu_msg *msg) in imx_mu_receive_msg() argument
57 assert(base && msg); in imx_mu_receive_msg()
60 res = imx_mu_plat_receive(base, 0, &response); in imx_mu_receive_msg()
76 nb_channel = imx_mu_plat_get_rx_channel(base); in imx_mu_receive_msg()
79 res = imx_mu_plat_receive(base, count % nb_channel, in imx_mu_receive_msg()
94 static TEE_Result imx_mu_send_msg(vaddr_t base, struct imx_mu_msg *msg) in imx_mu_send_msg() argument
103 assert(base && msg); in imx_mu_send_msg()
[all …]
/optee_os/core/drivers/clk/sam/
H A Dat91_main.c34 vaddr_t base; member
39 uint32_t status = io_read32(osc->base + AT91_PMC_SR); in pmc_main_rc_osc_ready()
47 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_enable()
51 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_enable()
65 uint32_t mor = io_read32(osc->base + AT91_CKGR_MOR); in pmc_main_rc_osc_disable()
70 io_clrsetbits32(osc->base + AT91_CKGR_MOR, in pmc_main_rc_osc_disable()
105 osc->base = pmc->base; in pmc_register_main_rc_osc()
123 uint32_t status = io_read32(pmc->base + AT91_PMC_SR); in pmc_main_osc_ready()
131 uint32_t mor = io_read32(pmc->base + AT91_CKGR_MOR); in pmc_main_osc_enable()
140 io_write32(pmc->base + AT91_CKGR_MOR, mor); in pmc_main_osc_enable()
[all …]
/optee_os/core/drivers/crypto/stm32/
H A Dstm32_pka.c689 vaddr_t base; member
700 static TEE_Result pka_wait_bit(const vaddr_t base, const uint32_t bit_mask) in pka_wait_bit() argument
704 if (IO_READ32_POLL_TIMEOUT(base + _PKA_SR, value, in pka_wait_bit()
714 static void pka_disable(const vaddr_t base) in pka_disable() argument
716 io_clrbits32(base + _PKA_CR, _PKA_CR_EN); in pka_disable()
719 static TEE_Result pka_enable(const vaddr_t base, const uint32_t mode) in pka_enable() argument
722 io_clrsetbits32(base + _PKA_CR, _PKA_IT_MASK | _PKA_CR_MODE_MASK, in pka_enable()
725 io_setbits32(base + _PKA_CR, _PKA_CR_EN); in pka_enable()
727 return pka_wait_bit(base, _PKA_SR_INITOK); in pka_enable()
735 static TEE_Result stm32_pka_process(const vaddr_t base) in stm32_pka_process() argument
[all …]
/optee_os/core/arch/arm/plat-sam/
H A Dmatrix.c45 static void matrix_write(unsigned int base, in matrix_write() argument
49 io_write32(offset + base, value); in matrix_write()
52 static unsigned int matrix_read(int base, unsigned int offset) in matrix_read() argument
54 return io_read32(offset + base); in matrix_read()
113 unsigned int base = matrix_base(matrix); in matrix_set_periph_world() local
118 spselr = matrix_read(base, MATRIX_SPSELR(idx)); in matrix_set_periph_world()
123 matrix_write(base, MATRIX_SPSELR(idx), spselr); in matrix_set_periph_world()
196 static void matrix_save_regs(vaddr_t base, struct matrix_state *state) in matrix_save_regs() argument
201 state->spselr[idx] = matrix_read(base, MATRIX_SPSELR(idx)); in matrix_save_regs()
204 state->ssr[idx] = matrix_read(base, MATRIX_SSR(idx)); in matrix_save_regs()
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