62 	return io_pa_or_va(&pd->base, UART_SIZE);  in chip_to_base()
67 	vaddr_t base = chip_to_base(chip);  in mvebu_uart_flush()  local
76 	while (!(io_read32(base + UART_STATUS_REG) & UARTLSR_TXFIFOEMPTY))  in mvebu_uart_flush()
82 	vaddr_t base = chip_to_base(chip);  in mvebu_uart_have_rx_data()  local
84 	return (io_read32(base + UART_STATUS_REG) & UART_RX_READY);  in mvebu_uart_have_rx_data()
89 	vaddr_t base = chip_to_base(chip);  in mvebu_uart_getchar()  local
93 	return io_read32(base + UART_RX_REG) & 0xff;  in mvebu_uart_getchar()
98 	vaddr_t base = chip_to_base(chip);  in mvebu_uart_putc()  local
103 		tmp = io_read32(base + UART_STATUS_REG);  in mvebu_uart_putc()
107 	io_write32(base + UART_TX_REG, ch);  in mvebu_uart_putc()
121 	vaddr_t base;  in mvebu_uart_init()  local
124 	pd->base.pa = pbase;  in mvebu_uart_init()
127 	base = io_pa_or_va(&pd->base, UART_SIZE);  in mvebu_uart_init()
132 	io_clrsetbits32(base + UART_BAUD_REG, 0x3FF, dll);  in mvebu_uart_init()
135 	io_write32(base + UART_POSSR_REG, 0);  in mvebu_uart_init()
138 	io_write32(base + UART_CTRL_REG,  in mvebu_uart_init()
142 	io_write32(base + UART_CTRL_REG, 0);  in mvebu_uart_init()