30 	return io_pa_or_va(&pd->base, SIFIVE_UART_REG_SIZE);  in chip_to_base()
35 	vaddr_t base = chip_to_base(chip);  in sifive_uart_flush()  local
37 	while (io_read32(base + UART_REG_TXFIFO) & UART_TXFIFO_FULL) {  in sifive_uart_flush()
45 	vaddr_t base = chip_to_base(chip);  in sifive_uart_have_rx_data()  local
47 	return !(io_read32(base + UART_REG_RXFIFO) & UART_RXFIFO_EMPTY);  in sifive_uart_have_rx_data()
52 	vaddr_t base = chip_to_base(chip);  in sifive_uart_getchar()  local
58 	return io_read32(base + UART_REG_RXFIFO) & UART_RXFIFO_DATA;  in sifive_uart_getchar()
63 	vaddr_t base = chip_to_base(chip);  in sifive_uart_putc()  local
68 	io_write32(base + UART_REG_TXFIFO, ch);  in sifive_uart_putc()
78 void sifive_uart_init(struct sifive_uart_data *pd, paddr_t base,  in sifive_uart_init()  argument
83 	pd->base.pa = base;  in sifive_uart_init()
89 		io_write32(base + UART_REG_DIV, divisor);  in sifive_uart_init()
93 	io_write32(base + UART_REG_IE, 0);  in sifive_uart_init()
96 	io_write32(base + UART_REG_TXCTRL, UART_TXCTRL_TXEN);  in sifive_uart_init()
99 	io_write32(base + UART_REG_RXCTRL, UART_RXCTRL_RXEN);  in sifive_uart_init()