85 	return io_pa_or_va(&pd->base, PL011_REG_SIZE);  in chip_to_base()
90 	vaddr_t base = chip_to_base(chip);  in pl011_flush()  local
99 	while ((io_read32(base + UART_CR) & UART_CR_UARTEN) &&  in pl011_flush()
100 	       !(io_read32(base + UART_FR) & UART_FR_TXFE))  in pl011_flush()
106 	vaddr_t base = chip_to_base(chip);  in pl011_have_rx_data()  local
108 	return !(io_read32(base + UART_FR) & UART_FR_RXFE);  in pl011_have_rx_data()
113 	vaddr_t base = chip_to_base(chip);  in pl011_getchar()  local
117 	return io_read32(base + UART_DR) & 0xff;  in pl011_getchar()
122 	vaddr_t base = chip_to_base(chip);  in pl011_putc()  local
125 	while (io_read32(base + UART_FR) & UART_FR_TXFF)  in pl011_putc()
129 	io_write32(base + UART_DR, ch);  in pl011_putc()
134 	vaddr_t base = chip_to_base(chip);  in pl011_rx_intr_enable()  local
136 	io_write32(base + UART_IMSC, UART_IMSC_RXIM);  in pl011_rx_intr_enable()
141 	vaddr_t base = chip_to_base(chip);  in pl011_rx_intr_disable()  local
143 	io_write32(base + UART_IMSC, 0);  in pl011_rx_intr_disable()
159 	vaddr_t base;  in pl011_init()  local
161 	pd->base.pa = pbase;  in pl011_init()
164 	base = io_pa_or_va(&pd->base, PL011_REG_SIZE);  in pl011_init()
167 	io_write32(base + UART_RSR_ECR, 0);  in pl011_init()
169 	io_write32(base + UART_CR, 0);  in pl011_init()
174 		io_write32(base + UART_IBRD, divisor >> 6);  in pl011_init()
175 		io_write32(base + UART_FBRD, divisor & 0x3f);  in pl011_init()
179 	io_write32(base + UART_LCR_H, UART_LCRH_WLEN_8);  in pl011_init()
182 	io_write32(base + UART_IMSC, UART_IMSC_RXIM);  in pl011_init()
185 	io_write32(base + UART_CR, UART_CR_UARTEN | UART_CR_TXE | UART_CR_RXE);  in pl011_init()