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Searched refs:MEM_AREA_IO_NSEC (Results 1 – 25 of 37) sorted by relevance

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/optee_os/core/arch/arm/plat-hikey/
H A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
27 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMUSSI_BASE, PMUSSI_REG_SIZE);
30 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PERI_BASE, PERI_BASE_REG_SIZE);
31 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX0_BASE, PMX0_REG_SIZE);
32 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PMX1_BASE, PMX1_REG_SIZE);
33 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GPIO6_BASE, PL061_REG_SIZE);
34 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, SPI_BASE, PL022_REG_SIZE);
56 vaddr_t peri_base = core_mmu_get_va(PERI_BASE, MEM_AREA_IO_NSEC, in spi_init()
58 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_init()
60 vaddr_t pmx1_base = core_mmu_get_va(PMX1_BASE, MEM_AREA_IO_NSEC, in spi_init()
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H A Dspi_test.c23 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
25 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_cs_callback()
50 vaddr_t pmx0_base = core_mmu_get_va(PMX0_BASE, MEM_AREA_IO_NSEC, in spi_set_cs_mux()
71 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_manual_cs_control()
160 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_registered_cs_cb()
207 vaddr_t gpio6_base = core_mmu_get_va(GPIO6_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
209 vaddr_t spi_base = core_mmu_get_va(SPI_BASE, MEM_AREA_IO_NSEC, in spi_test_with_builtin_cs_control()
/optee_os/core/arch/arm/plat-bcm/
H A Dmain.c35 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, BCM_DEVICE5_BASE, BCM_DEVICE5_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, CFG_BCM_ELOG_AP_UART_LOG_BASE,
/optee_os/core/arch/arm/plat-ls/
H A Dmain.c59 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
72 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, DCFG_BASE, CORE_MMU_PGDIR_SIZE);
174 MEM_AREA_IO_NSEC, 1); in get_gic_offset()
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dmain.c37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB1_BASE, APB1_SIZE);
38 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB2_BASE, APB2_SIZE);
39 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB3_BASE, APB3_SIZE);
40 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB4_BASE, APB4_SIZE);
41 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, APB5_BASE, APB5_SIZE);
42 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB4_BASE, AHB4_SIZE);
43 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, AHB5_BASE, AHB5_SIZE);
403 uint8_t *va = phys_to_virt(nsec_start, MEM_AREA_IO_NSEC, in configure_sysram()
/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2600.c46 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, SMALL_PAGE_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, SCU_BASE, SMALL_PAGE_SIZE);
/optee_os/core/arch/arm/plat-imx/
H A Dimx_pl310.c26 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
89 return core_mmu_get_va(PL310_BASE, MEM_AREA_IO_NSEC, 1); in pl310_nsbase()
H A Dmain.c45 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os/core/arch/arm/plat-d02/
H A Dmain.c16 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os/core/arch/arm/plat-rpi3/
H A Dmain.c37 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/riscv/plat-sifive/
H A Dmain.c11 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/arm/plat-rpi5/
H A Dmain.c10 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/arm/plat-d06/
H A Dmain.c12 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, LPC_BASE, LPC_SIZE);
/optee_os/core/arch/arm/plat-poplar/
H A Dmain.c19 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
/optee_os/core/drivers/bnxt/
H A Dbnxt_images.c101 phys_to_virt(QSPI_BNXT_IMG, MEM_AREA_IO_NSEC, in get_bnxt_images_info()
112 MEM_AREA_IO_NSEC, in get_bnxt_images_info()
/optee_os/core/arch/arm/plat-sprd/
H A Dmain.c36 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/arm/plat-hisilicon/
H A Dmain.c16 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
/optee_os/core/arch/arm/plat-rockchip/
H A Dmain.c19 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/arm/plat-mediatek/
H A Dmain.c16 register_phys_mem_pgdir(MEM_AREA_IO_NSEC,
/optee_os/core/arch/arm/plat-qcom/
H A Dmain.c18 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, GENI_UART_REG_BASE,
/optee_os/core/drivers/crypto/aspeed/
H A Dcrypto_ast2600.c28 scu_virt = core_mmu_get_va(SCU_BASE, MEM_AREA_IO_NSEC, SMALL_PAGE_SIZE); in crypto_ast2600_init()
/optee_os/core/arch/arm/plat-synquacer/
H A Dmain.c25 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE,
/optee_os/core/arch/riscv/plat-virt/
H A Dmain.c17 register_phys_mem_pgdir(MEM_AREA_IO_NSEC, UART0_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/riscv/plat-spike/drivers/
H A Dhtif.c17 register_phys_mem(MEM_AREA_IO_NSEC, HTIF_BASE,
/optee_os/core/lib/scmi-server/
H A Dscmi_server.c24 return (uintptr_t)phys_to_virt(pa, MEM_AREA_IO_NSEC, sz); in smt_phys_to_virt()

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