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Searched refs:slcr_base (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A Dslcr.c93 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); in zynq_slcr_lock()
101 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); in zynq_slcr_unlock()
121 clrbits_le32(&slcr_base->reboot_status, 0xF000000); in zynq_slcr_cpu_reset()
123 writel(1, &slcr_base->pss_rst_ctrl); in zynq_slcr_cpu_reset()
133 writel(0xF, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_disable()
136 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
138 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
141 writel(0xA, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
151 writel(0xF, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_enable()
154 writel(0x0, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_enable()
[all …]
H A Dcpu.c29 writel(0x1F, &slcr_base->ocm_cfg); in arch_cpu_init()
31 writel(0x0, &slcr_base->fpga_rst_ctrl); in arch_cpu_init()
33 writel(0x0, &slcr_base->ddr_urgent_sel); in arch_cpu_init()
35 writel(0xC, &slcr_base->ddr_urgent); in arch_cpu_init()
/OK3568_Linux_fs/u-boot/drivers/clk/
H A Dclk_zynq.c60 return &slcr_base->arm_pll_ctrl; in zynq_clk_get_register()
62 return &slcr_base->ddr_pll_ctrl; in zynq_clk_get_register()
64 return &slcr_base->io_pll_ctrl; in zynq_clk_get_register()
66 return &slcr_base->lqspi_clk_ctrl; in zynq_clk_get_register()
68 return &slcr_base->smc_clk_ctrl; in zynq_clk_get_register()
70 return &slcr_base->pcap_clk_ctrl; in zynq_clk_get_register()
72 return &slcr_base->sdio_clk_ctrl; in zynq_clk_get_register()
74 return &slcr_base->uart_clk_ctrl; in zynq_clk_get_register()
76 return &slcr_base->spi_clk_ctrl; in zynq_clk_get_register()
79 return &slcr_base->dci_clk_ctrl; in zynq_clk_get_register()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/zynqmp/
H A Dslcr.c53 val = readl(&slcr_base->mio_pin in zynq_slcr_get_mio_pin_status()
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-zynqmp/
H A Dhardware.h86 #define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR) macro
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/include/mach/
H A Dhardware.h94 #define slcr_base ((struct slcr_regs *)ZYNQ_SYS_CTRL_BASEADDR) macro