1 /*
2 * Copyright (C) 2012 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2012 Xilinx, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7 #include <common.h>
8 #include <asm/io.h>
9 #include <asm/arch/clk.h>
10 #include <asm/arch/sys_proto.h>
11 #include <asm/arch/hardware.h>
12
13 #define ZYNQ_SILICON_VER_MASK 0xF0000000
14 #define ZYNQ_SILICON_VER_SHIFT 28
15
arch_cpu_init(void)16 int arch_cpu_init(void)
17 {
18 zynq_slcr_unlock();
19 #ifndef CONFIG_SPL_BUILD
20 /* Device config APB, unlock the PCAP */
21 writel(0x757BDF0D, &devcfg_base->unlock);
22 writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
23
24 #if (CONFIG_SYS_SDRAM_BASE == 0)
25 /* remap DDR to zero, FILTERSTART */
26 writel(0, &scu_base->filter_start);
27
28 /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
29 writel(0x1F, &slcr_base->ocm_cfg);
30 /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
31 writel(0x0, &slcr_base->fpga_rst_ctrl);
32 /* Set urgent bits with register */
33 writel(0x0, &slcr_base->ddr_urgent_sel);
34 /* Urgent write, ports S2/S3 */
35 writel(0xC, &slcr_base->ddr_urgent);
36 #endif
37 #endif
38 zynq_slcr_lock();
39
40 return 0;
41 }
42
zynq_get_silicon_version(void)43 unsigned int zynq_get_silicon_version(void)
44 {
45 return (readl(&devcfg_base->mctrl) & ZYNQ_SILICON_VER_MASK)
46 >> ZYNQ_SILICON_VER_SHIFT;
47 }
48
reset_cpu(ulong addr)49 void reset_cpu(ulong addr)
50 {
51 zynq_slcr_cpu_reset();
52 while (1)
53 ;
54 }
55
56 #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)57 void enable_caches(void)
58 {
59 /* Enable D-cache. I-cache is already enabled in start.S */
60 dcache_enable();
61 }
62 #endif
63