60 		return &slcr_base->arm_pll_ctrl;  in zynq_clk_get_register()
62 		return &slcr_base->ddr_pll_ctrl;  in zynq_clk_get_register()
64 		return &slcr_base->io_pll_ctrl;  in zynq_clk_get_register()
66 		return &slcr_base->lqspi_clk_ctrl;  in zynq_clk_get_register()
68 		return &slcr_base->smc_clk_ctrl;  in zynq_clk_get_register()
70 		return &slcr_base->pcap_clk_ctrl;  in zynq_clk_get_register()
72 		return &slcr_base->sdio_clk_ctrl;  in zynq_clk_get_register()
74 		return &slcr_base->uart_clk_ctrl;  in zynq_clk_get_register()
76 		return &slcr_base->spi_clk_ctrl;  in zynq_clk_get_register()
79 		return &slcr_base->dci_clk_ctrl;  in zynq_clk_get_register()
81 		return &slcr_base->gem0_clk_ctrl;  in zynq_clk_get_register()
83 		return &slcr_base->gem1_clk_ctrl;  in zynq_clk_get_register()
85 		return &slcr_base->fpga0_clk_ctrl;  in zynq_clk_get_register()
87 		return &slcr_base->fpga1_clk_ctrl;  in zynq_clk_get_register()
89 		return &slcr_base->fpga2_clk_ctrl;  in zynq_clk_get_register()
91 		return &slcr_base->fpga3_clk_ctrl;  in zynq_clk_get_register()
93 		return &slcr_base->can_clk_ctrl;  in zynq_clk_get_register()
98 		return &slcr_base->dbg_clk_ctrl;  in zynq_clk_get_register()
158 		clk_ctrl = readl(&slcr_base->gem0_rclk_ctrl);  in zynq_clk_get_gem_rclk()
160 		clk_ctrl = readl(&slcr_base->gem1_rclk_ctrl);  in zynq_clk_get_gem_rclk()
175 	clk_ctrl = readl(&slcr_base->arm_clk_ctrl);  in zynq_clk_get_cpu_rate()
184 		clk_621 = readl(&slcr_base->clk_621_true) & 1;  in zynq_clk_get_cpu_rate()
206 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr2x_rate()
218 	clk_ctrl = readl(&slcr_base->ddr_clk_ctrl);  in zynq_clk_get_ddr3x_rate()
230 	clk_ctrl = readl(&slcr_base->dci_clk_ctrl);  in zynq_clk_get_dci_rate()