1 /* 2 * (C) Copyright 2014 - 2015 Xilinx, Inc. 3 * Michal Simek <michal.simek@xilinx.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <malloc.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/arch/clk.h> 14 15 /* 16 * zynq_slcr_mio_get_status - Get the status of MIO peripheral. 17 * 18 * @peri_name: Name of the peripheral for checking MIO status 19 * @get_pins: Pointer to array of get pin for this peripheral 20 * @num_pins: Number of pins for this peripheral 21 * @mask: Mask value 22 * @check_val: Required check value to get the status of periph 23 */ 24 struct zynq_slcr_mio_get_status { 25 const char *peri_name; 26 const int *get_pins; 27 int num_pins; 28 u32 mask; 29 u32 check_val; 30 }; 31 32 static const struct zynq_slcr_mio_get_status mio_periphs[] = { 33 }; 34 35 /* 36 * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral. 37 * 38 * @periph: Name of the peripheral 39 * 40 * Returns count to indicate the number of pins configured for the 41 * given @periph. 42 */ zynq_slcr_get_mio_pin_status(const char * periph)43int zynq_slcr_get_mio_pin_status(const char *periph) 44 { 45 const struct zynq_slcr_mio_get_status *mio_ptr; 46 int val, i, j; 47 int mio = 0; 48 49 for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) { 50 if (strcmp(periph, mio_periphs[i].peri_name) == 0) { 51 mio_ptr = &mio_periphs[i]; 52 for (j = 0; j < mio_ptr->num_pins; j++) { 53 val = readl(&slcr_base->mio_pin 54 [mio_ptr->get_pins[j]]); 55 if ((val & mio_ptr->mask) == mio_ptr->check_val) 56 mio++; 57 } 58 break; 59 } 60 } 61 62 return mio; 63 } 64