Lines Matching refs:slcr_base
93 writel(SLCR_LOCK_MAGIC, &slcr_base->slcr_lock); in zynq_slcr_lock()
101 writel(SLCR_UNLOCK_MAGIC, &slcr_base->slcr_unlock); in zynq_slcr_unlock()
121 clrbits_le32(&slcr_base->reboot_status, 0xF000000); in zynq_slcr_cpu_reset()
123 writel(1, &slcr_base->pss_rst_ctrl); in zynq_slcr_cpu_reset()
133 writel(0xF, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_disable()
136 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
138 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
141 writel(0xA, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
151 writel(0xF, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_enable()
154 writel(0x0, &slcr_base->fpga_rst_ctrl); in zynq_slcr_devcfg_enable()
162 return readl(&slcr_base->boot_mode); in zynq_slcr_get_boot_mode()
167 return (readl(&slcr_base->pss_idcode) & SLCR_IDCODE_MASK) >> in zynq_slcr_get_idcode()
189 val = readl(&slcr_base->mio_pin in zynq_slcr_get_mio_pin_status()