xref: /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/zynqmp/slcr.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2014 - 2015 Xilinx, Inc.
3*4882a593Smuzhiyun  * Michal Simek <michal.simek@xilinx.com>
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <asm/arch/hardware.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun #include <asm/arch/clk.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun /*
16*4882a593Smuzhiyun  * zynq_slcr_mio_get_status - Get the status of MIO peripheral.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * @peri_name: Name of the peripheral for checking MIO status
19*4882a593Smuzhiyun  * @get_pins: Pointer to array of get pin for this peripheral
20*4882a593Smuzhiyun  * @num_pins: Number of pins for this peripheral
21*4882a593Smuzhiyun  * @mask: Mask value
22*4882a593Smuzhiyun  * @check_val: Required check value to get the status of  periph
23*4882a593Smuzhiyun  */
24*4882a593Smuzhiyun struct zynq_slcr_mio_get_status {
25*4882a593Smuzhiyun 	const char *peri_name;
26*4882a593Smuzhiyun 	const int *get_pins;
27*4882a593Smuzhiyun 	int num_pins;
28*4882a593Smuzhiyun 	u32 mask;
29*4882a593Smuzhiyun 	u32 check_val;
30*4882a593Smuzhiyun };
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static const struct zynq_slcr_mio_get_status mio_periphs[] = {
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun  * zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
37*4882a593Smuzhiyun  *
38*4882a593Smuzhiyun  * @periph: Name of the peripheral
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  * Returns count to indicate the number of pins configured for the
41*4882a593Smuzhiyun  * given @periph.
42*4882a593Smuzhiyun  */
zynq_slcr_get_mio_pin_status(const char * periph)43*4882a593Smuzhiyun int zynq_slcr_get_mio_pin_status(const char *periph)
44*4882a593Smuzhiyun {
45*4882a593Smuzhiyun 	const struct zynq_slcr_mio_get_status *mio_ptr;
46*4882a593Smuzhiyun 	int val, i, j;
47*4882a593Smuzhiyun 	int mio = 0;
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
50*4882a593Smuzhiyun 		if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
51*4882a593Smuzhiyun 			mio_ptr = &mio_periphs[i];
52*4882a593Smuzhiyun 			for (j = 0; j < mio_ptr->num_pins; j++) {
53*4882a593Smuzhiyun 				val = readl(&slcr_base->mio_pin
54*4882a593Smuzhiyun 						[mio_ptr->get_pins[j]]);
55*4882a593Smuzhiyun 				if ((val & mio_ptr->mask) == mio_ptr->check_val)
56*4882a593Smuzhiyun 					mio++;
57*4882a593Smuzhiyun 			}
58*4882a593Smuzhiyun 			break;
59*4882a593Smuzhiyun 		}
60*4882a593Smuzhiyun 	}
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun 	return mio;
63*4882a593Smuzhiyun }
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