Home
last modified time | relevance | path

Searched refs:lane_count (Results 1 – 25 of 62) sorted by relevance

123

/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Danalogix_dp.c98 int lane, lane_count, retval; in analogix_dp_link_start() local
100 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
105 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
110 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
114 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
128 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
144 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
149 lane_count, buf); in analogix_dp_link_start()
162 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
167 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
[all …]
H A Ddrm_dp_helper.c53 int lane_count) in drm_dp_channel_eq_ok() argument
63 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
72 int lane_count) in drm_dp_clock_recovery_ok() argument
77 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
105 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
106 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
132 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
134 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
141 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
197 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
245 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { in intel_dp_link_training_clock_recovery()
366 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
375 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
[all …]
H A Dintel_dpio_phy.c579 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
581 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
589 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
669 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
682 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
690 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
698 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
721 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
735 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
761 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
[all …]
H A Dvlv_dsi.c43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
47 8 * 100), lane_count); in txbyteclkhs()
51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1083 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1135 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1137 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1139 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1189 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1191 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
[all …]
H A Dintel_dp.h47 int link_rate, u8 lane_count,
50 int link_rate, u8 lane_count);
128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
130 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
H A Dvlv_dsi_pll.c44 int lane_count) in dsi_clk_from_pclk() argument
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
125 intel_dsi->lane_count); in vlv_dsi_pll_compute()
316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_get_pclk()
337 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_get_pclk()
467 intel_dsi->lane_count); in bxt_dsi_pll_compute()
H A Dintel_combo_phy.c303 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
311 switch (lane_count) { in intel_combo_phy_power_up_lanes()
322 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
329 switch (lane_count) { in intel_combo_phy_power_up_lanes()
339 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
H A Dintel_dp.c413 u8 lane_count) in intel_dp_link_params_valid() argument
424 if (lane_count == 0 || in intel_dp_link_params_valid()
425 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
433 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
440 max_rate = intel_dp_max_data_rate(link_rate, lane_count); in intel_dp_can_link_train_fallback_for_edp()
448 int link_rate, u8 lane_count) in intel_dp_get_link_train_fallback_values() argument
469 lane_count)) { in intel_dp_get_link_train_fallback_values()
475 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
476 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
480 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
[all …]
H A Dintel_combo_phy.h18 int lane_count, bool lane_reversal);
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c166 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
200 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
210 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
326 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
343 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); in dpcd_set_lt_pattern_and_lane_settings()
431 for (lane = 0; lane < src.link_settings.lane_count; lane++) { in update_drive_settings()
493 for (lane = 1; lane < link_training_setting->link_settings.lane_count; in find_max_drive_settings()
551 max_lt_setting->link_settings.lane_count = in find_max_drive_settings()
552 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
557 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/tegra124/
H A Ddp.c434 link_cfg->lane_count); in tegra_dc_dp_dump_link_cfg()
459 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
465 if (cfg->lane_count == 1) { in _tegra_dp_lower_link_config()
467 cfg->lane_count = cfg->max_lane_count; in _tegra_dp_lower_link_config()
469 cfg->lane_count /= 2; in _tegra_dp_lower_link_config()
477 return (cfg->lane_count > 0) ? 0 : -ENOLINK; in _tegra_dp_lower_link_config()
510 if (!link_rate || !link_cfg->lane_count || !timing->pixelclock.typ || in tegra_dc_dp_calc_config()
515 (u64)link_rate * 8 * link_cfg->lane_count) in tegra_dc_dp_calc_config()
523 do_div(ratio_f, link_rate * link_cfg->lane_count); in tegra_dc_dp_calc_config()
603 (8 * link_cfg->lane_count); in tegra_dc_dp_calc_config()
[all …]
H A Dsor.c215 u32 lane_count, int pu) in tegra_dc_sor_power_dplanes() argument
223 switch (lane_count) { in tegra_dc_sor_power_dplanes()
234 debug("dp: invalid lane number %d\n", lane_count); in tegra_dc_sor_power_dplanes()
239 tegra_dc_sor_set_lane_count(dev, lane_count); in tegra_dc_sor_power_dplanes()
390 u8 *lane_count) in tegra_dc_sor_read_link_config() argument
403 *lane_count = 0; in tegra_dc_sor_read_link_config()
406 *lane_count = 1; in tegra_dc_sor_read_link_config()
409 *lane_count = 2; in tegra_dc_sor_read_link_config()
412 *lane_count = 4; in tegra_dc_sor_read_link_config()
428 void tegra_dc_sor_set_lane_count(struct udevice *dev, u8 lane_count) in tegra_dc_sor_set_lane_count() argument
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c327 int lane, lane_count, retval; in analogix_dp_link_start() local
329 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
334 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
339 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
343 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
365 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
381 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
386 lane_count); in analogix_dp_link_start()
401 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
406 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_edp.c329 values[1] = edp->link_train.lane_count; in rk_edp_link_configure()
340 for (i = 0; i < edp->link_train.lane_count; i++) in rk_edp_set_link_training()
365 static int rk_edp_clock_recovery(const u8 *link_status, int lane_count) in rk_edp_clock_recovery() argument
370 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
379 static int rk_edp_channel_eq(const u8 *link_status, int lane_count) in rk_edp_channel_eq() argument
389 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
421 static void edp_get_adjust_train(const u8 *link_status, int lane_count, in edp_get_adjust_train() argument
428 for (lane = 0; lane < lane_count; lane++) { in edp_get_adjust_train()
487 edp->link_train.lane_count); in rk_edp_link_train_cr()
500 edp->link_train.lane_count); in rk_edp_link_train_cr()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c266 uint8_t lane_count; member
902 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
915 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
917 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
921 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
925 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
933 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
938 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
995 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1012 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
[all …]
H A Dmdfld_dsi_dpi.c474 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
489 val = lane_count; in mdfld_dsi_dpi_controller_init()
510 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
527 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
753 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
777 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
791 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h91 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
93 return (lane_count == 1 || in is_lane_count_valid()
94 lane_count == 2 || in is_lane_count_valid()
95 lane_count == 4); in is_lane_count_valid()
H A Ddp_audio.h21 u32 lane_count; member
/OK3568_Linux_fs/kernel/drivers/gpu/drm/panel/
H A Dpanel-maxim-max96772.c33 u32 lane_count; member
55 u32 lane_count; member
164 maxim_deserializer_write(p, 0xe792, p->lane_count); in max96772_prepare()
174 p->link_rate, p->lane_count, p->ssc); in max96772_prepare()
227 hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - p->lane_count; in max96772_prepare()
294 if (!p->desc->link_rate || !p->desc->lane_count) { in max96772_panel_prepare()
304 p->lane_count = min_t(int, 4, dpcd & DP_MAX_LANE_COUNT_MASK); in max96772_panel_prepare()
323 p->lane_count = p->desc->lane_count; in max96772_panel_prepare()
517 .lane_count = 4,
/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c55 u32 lane_count; member
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
500 &ps8622->lane_count)) { in ps8622_probe()
501 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
502 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
505 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
/OK3568_Linux_fs/kernel/include/linux/phy/
H A Dphy-rockchip-typec.h13 int tcphy_dp_set_lane_count(struct phy *phy, u8 lane_count);
22 static inline int tcphy_dp_set_lane_count(struct phy *phy, u8 lane_count) in tcphy_dp_set_lane_count() argument
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c202 link->cur_link_settings.lane_count, in dp_link_settings_read()
209 link->verified_link_cap.lane_count, in dp_link_settings_read()
216 link->reported_link_cap.lane_count, in dp_link_settings_read()
223 link->preferred_link_setting.lane_count, in dp_link_settings_read()
314 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
457 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
458 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
464 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
465 link->cur_link_settings.lane_count; in dp_phy_settings_write()
473 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c608 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
622 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder()
1143 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1182 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1222 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output()
1261 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output()
1342 cntl.lanes_number = link_settings->link_settings.lane_count; in dce110_link_encoder_dp_set_lane_settings()
1347 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_link_encoder.c221 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
281 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn20_link_encoder_get_max_link_cap()

123