1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2022 Rockchip Electronics Co. Ltd.
4 */
5
6 #include <linux/backlight.h>
7 #include <linux/delay.h>
8 #include <linux/gpio/consumer.h>
9 #include <linux/of_platform.h>
10 #include <linux/pinctrl/consumer.h>
11 #include <linux/i2c.h>
12 #include <linux/module.h>
13 #include <linux/regmap.h>
14 #include <linux/of.h>
15
16 #include <video/videomode.h>
17 #include <video/of_display_timing.h>
18 #include <video/display_timing.h>
19 #include <uapi/linux/media-bus-format.h>
20
21 #include <drm/drm_device.h>
22 #include <drm/drm_dp_helper.h>
23 #include <drm/drm_modes.h>
24 #include <drm/drm_panel.h>
25
26 struct max96772_panel;
27
28 struct panel_desc {
29 const char *name;
30 u32 width_mm;
31 u32 height_mm;
32 u32 link_rate;
33 u32 lane_count;
34 bool ssc;
35
36 int (*prepare)(struct max96772_panel *p);
37 int (*unprepare)(struct max96772_panel *p);
38 int (*enable)(struct max96772_panel *p);
39 int (*disable)(struct max96772_panel *p);
40 int (*backlight_enable)(struct max96772_panel *p);
41 int (*backlight_disable)(struct max96772_panel *p);
42 };
43
44 struct max96772_panel {
45 struct drm_panel panel;
46 struct device *dev;
47 struct {
48 struct regmap *serializer;
49 struct regmap *deserializer;
50 } regmap;
51 struct backlight_device *backlight;
52 struct drm_display_mode mode;
53 const struct panel_desc *desc;
54 u32 link_rate;
55 u32 lane_count;
56 bool ssc;
57 bool panel_dual_link;
58 };
59
60 #define maxim_serializer_write(p, reg, val) do { \
61 int ret; \
62 ret = regmap_write(p->regmap.serializer, reg, val); \
63 if (ret) \
64 return ret; \
65 } while (0)
66
67 #define maxim_serializer_read(p, reg, val) do { \
68 int ret; \
69 ret = regmap_read(p->regmap.serializer, reg, val); \
70 if (ret) \
71 return ret; \
72 } while (0)
73
74 #define maxim_deserializer_write(p, reg, val) do { \
75 int ret; \
76 ret = regmap_write(p->regmap.deserializer, reg, val); \
77 if (ret) \
78 return ret; \
79 } while (0)
80
81 #define maxim_deserializer_read(p, reg, val) do { \
82 int ret; \
83 ret = regmap_read(p->regmap.deserializer, reg, val); \
84 if (ret) \
85 return ret; \
86 } while (0)
87
88 static const struct reg_sequence max96772_clk_ref[3][14] = {
89 {
90 { 0xe7b2, 0x50 },
91 { 0xe7b3, 0x00 },
92 { 0xe7b4, 0xcc },
93 { 0xe7b5, 0x44 },
94 { 0xe7b6, 0x81 },
95 { 0xe7b7, 0x30 },
96 { 0xe7b8, 0x07 },
97 { 0xe7b9, 0x10 },
98 { 0xe7ba, 0x01 },
99 { 0xe7bb, 0x00 },
100 { 0xe7bc, 0x00 },
101 { 0xe7bd, 0x00 },
102 { 0xe7be, 0x52 },
103 { 0xe7bf, 0x00 },
104 }, {
105 { 0xe7b2, 0x50 },
106 { 0xe7b3, 0x00 },
107 { 0xe7b4, 0x00 },
108 { 0xe7b5, 0x40 },
109 { 0xe7b6, 0x6c },
110 { 0xe7b7, 0x20 },
111 { 0xe7b8, 0x07 },
112 { 0xe7b9, 0x00 },
113 { 0xe7ba, 0x01 },
114 { 0xe7bb, 0x00 },
115 { 0xe7bc, 0x00 },
116 { 0xe7bd, 0x00 },
117 { 0xe7be, 0x52 },
118 { 0xe7bf, 0x00 },
119 }, {
120 { 0xe7b2, 0x30 },
121 { 0xe7b3, 0x00 },
122 { 0xe7b4, 0x00 },
123 { 0xe7b5, 0x40 },
124 { 0xe7b6, 0x6c },
125 { 0xe7b7, 0x20 },
126 { 0xe7b8, 0x14 },
127 { 0xe7b9, 0x00 },
128 { 0xe7ba, 0x2e },
129 { 0xe7bb, 0x00 },
130 { 0xe7bc, 0x00 },
131 { 0xe7bd, 0x01 },
132 { 0xe7be, 0x32 },
133 { 0xe7bf, 0x00 },
134 }
135 };
136
max96772_aux_dpcd_read(struct max96772_panel * p,u32 reg,u32 * value)137 static int max96772_aux_dpcd_read(struct max96772_panel *p, u32 reg, u32 *value)
138 {
139 maxim_deserializer_write(p, 0xe778, reg & 0xff);
140 maxim_deserializer_write(p, 0xe779, (reg >> 8) & 0xff);
141 maxim_deserializer_write(p, 0xe77c, (reg >> 16) & 0xff);
142 maxim_deserializer_write(p, 0xe776, 0x10);
143 maxim_deserializer_write(p, 0xe777, 0x80);
144 /* FIXME */
145 msleep(50);
146 maxim_deserializer_read(p, 0xe77a, value);
147
148 return 0;
149 }
150
max96772_prepare(struct max96772_panel * p)151 static int max96772_prepare(struct max96772_panel *p)
152 {
153 const struct drm_display_mode *mode = &p->mode;
154 u32 hfp, hsa, hbp, hact;
155 u32 vact, vsa, vfp, vbp;
156 u64 hwords, mvid;
157 bool hsync_pol, vsync_pol;
158
159 if (p->panel_dual_link) {
160 maxim_deserializer_write(p, 0x0010, 0x00);
161 }
162
163 maxim_deserializer_write(p, 0xe790, p->link_rate);
164 maxim_deserializer_write(p, 0xe792, p->lane_count);
165
166 if (p->ssc) {
167 maxim_deserializer_write(p, 0xe7b0, 0x01);
168 maxim_deserializer_write(p, 0xe7b1, 0x10);
169 } else {
170 maxim_deserializer_write(p, 0xe7b1, 0x00);
171 }
172
173 dev_info(p->dev, "link_rate=0x%02x, lane_count=0x%02x, ssc=%d\n",
174 p->link_rate, p->lane_count, p->ssc);
175
176 switch (p->link_rate) {
177 case DP_LINK_BW_5_4:
178 regmap_multi_reg_write(p->regmap.deserializer, max96772_clk_ref[2],
179 ARRAY_SIZE(max96772_clk_ref[2]));
180 break;
181 case DP_LINK_BW_2_7:
182 regmap_multi_reg_write(p->regmap.deserializer, max96772_clk_ref[1],
183 ARRAY_SIZE(max96772_clk_ref[1]));
184 break;
185 case DP_LINK_BW_1_62:
186 default:
187 regmap_multi_reg_write(p->regmap.deserializer, max96772_clk_ref[0],
188 ARRAY_SIZE(max96772_clk_ref[0]));
189 break;
190 }
191
192 vact = mode->vdisplay;
193 vsa = mode->vsync_end - mode->vsync_start;
194 vfp = mode->vsync_start - mode->vdisplay;
195 vbp = mode->vtotal - mode->vsync_end;
196 hact = mode->hdisplay;
197 hsa = mode->hsync_end - mode->hsync_start;
198 hfp = mode->hsync_start - mode->hdisplay;
199 hbp = mode->htotal - mode->hsync_end;
200
201 maxim_deserializer_write(p, 0xe794, hact & 0xff);
202 maxim_deserializer_write(p, 0xe795, (hact >> 8) & 0xff);
203 maxim_deserializer_write(p, 0xe796, hfp & 0xff);
204 maxim_deserializer_write(p, 0xe797, (hfp >> 8) & 0xff);
205 maxim_deserializer_write(p, 0xe798, hsa & 0xff);
206 maxim_deserializer_write(p, 0xe799, (hsa >> 8) & 0xff);
207 maxim_deserializer_write(p, 0xe79a, hbp & 0xff);
208 maxim_deserializer_write(p, 0xe79b, (hbp >> 8) & 0xff);
209 maxim_deserializer_write(p, 0xe79c, vact & 0xff);
210 maxim_deserializer_write(p, 0xe79d, (vact >> 8) & 0xff);
211 maxim_deserializer_write(p, 0xe79e, vfp & 0xff);
212 maxim_deserializer_write(p, 0xe79f, (vfp >> 8) & 0xff);
213 maxim_deserializer_write(p, 0xe7a0, vsa & 0xff);
214 maxim_deserializer_write(p, 0xe7a1, (vsa >> 8) & 0xff);
215 maxim_deserializer_write(p, 0xe7a2, vbp & 0xff);
216 maxim_deserializer_write(p, 0xe7a3, (vbp >> 8) & 0xff);
217
218 hsync_pol = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
219 vsync_pol = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
220 maxim_deserializer_write(p, 0xe7ac, hsync_pol | (vsync_pol << 1));
221
222 /* NVID should always be set to 0x8000 */
223 maxim_deserializer_write(p, 0xe7a8, 0);
224 maxim_deserializer_write(p, 0xe7a9, 0x80);
225
226 /* HWORDS = ((HRES x bits / pixel) / 16) - LANE_COUNT */
227 hwords = DIV_ROUND_CLOSEST_ULL(hact * 24, 16) - p->lane_count;
228 maxim_deserializer_write(p, 0xe7a4, hwords);
229 maxim_deserializer_write(p, 0xe7a5, hwords >> 8);
230
231 /* MVID = (PCLK x NVID) x 10 / Link Rate */
232 mvid = DIV_ROUND_CLOSEST_ULL((u64)mode->clock * 32768,
233 drm_dp_bw_code_to_link_rate(p->link_rate));
234 maxim_deserializer_write(p, 0xe7a6, mvid & 0xff);
235 maxim_deserializer_write(p, 0xe7a7, (mvid >> 8) & 0xff);
236
237 maxim_deserializer_write(p, 0xe7aa, 0x40);
238 maxim_deserializer_write(p, 0xe7ab, 0x00);
239
240 /* set AUD_TX_EN = 0 */
241 maxim_deserializer_write(p, 0x02, 0xf3);
242 /* set AUD_EN_RX = 0 */
243 maxim_deserializer_write(p, 0x158, 0x20);
244 /* set MFP2 GPIO_TX_EN */
245 maxim_deserializer_write(p, 0x2b6, 0x03);
246
247 return 0;
248 }
249
max96776_enable(struct max96772_panel * p)250 static int max96776_enable(struct max96772_panel *p)
251 {
252 u32 status[2];
253 u32 val;
254 int ret;
255
256 /* Run link training */
257 maxim_deserializer_write(p, 0xe776, 0x02);
258 maxim_deserializer_write(p, 0xe777, 0x80);
259
260 ret = regmap_read_poll_timeout(p->regmap.deserializer, 0x07f0, val,
261 val & 0x01, MSEC_PER_SEC,
262 500 * MSEC_PER_SEC);
263 if (!ret)
264 return 0;
265
266 ret = max96772_aux_dpcd_read(p, DP_LANE0_1_STATUS, &status[0]);
267 if (ret)
268 return ret;
269
270 ret = max96772_aux_dpcd_read(p, DP_LANE2_3_STATUS, &status[1]);
271 if (ret)
272 return ret;
273
274 dev_err(p->dev, "Link Training failed: LANE0_1_STATUS=0x%02x, LANE2_3_STATUS=0x%02x\n",
275 status[0], status[1]);
276
277 return 0;
278 }
279
to_max96772_panel(struct drm_panel * panel)280 static inline struct max96772_panel *to_max96772_panel(struct drm_panel *panel)
281 {
282 return container_of(panel, struct max96772_panel, panel);
283 }
284
max96772_panel_prepare(struct drm_panel * panel)285 static int max96772_panel_prepare(struct drm_panel *panel)
286 {
287 struct max96772_panel *p = to_max96772_panel(panel);
288
289 pinctrl_pm_select_default_state(p->dev);
290
291 if (p->desc->prepare)
292 p->desc->prepare(p);
293
294 if (!p->desc->link_rate || !p->desc->lane_count) {
295 u32 dpcd;
296 int ret;
297
298 ret = max96772_aux_dpcd_read(p, DP_MAX_LANE_COUNT, &dpcd);
299 if (ret) {
300 dev_err(p->dev, "failed to read max lane count\n");
301 return ret;
302 }
303
304 p->lane_count = min_t(int, 4, dpcd & DP_MAX_LANE_COUNT_MASK);
305
306 ret = max96772_aux_dpcd_read(p, DP_MAX_LINK_RATE, &dpcd);
307 if (ret) {
308 dev_err(p->dev, "failed to read max link rate\n");
309 return ret;
310 }
311
312 p->link_rate = min_t(int, dpcd, DP_LINK_BW_5_4);
313
314 ret = max96772_aux_dpcd_read(p, DP_MAX_DOWNSPREAD, &dpcd);
315 if (ret) {
316 dev_err(p->dev, "failed to read max downspread\n");
317 return ret;
318 }
319
320 p->ssc = !!(dpcd & DP_MAX_DOWNSPREAD_0_5);
321 } else {
322 p->link_rate = p->desc->link_rate;
323 p->lane_count = p->desc->lane_count;
324 p->ssc = p->desc->ssc;
325 }
326
327 return max96772_prepare(p);
328 }
329
max96772_panel_unprepare(struct drm_panel * panel)330 static int max96772_panel_unprepare(struct drm_panel *panel)
331 {
332 struct max96772_panel *p = to_max96772_panel(panel);
333
334 if (p->desc->unprepare)
335 p->desc->unprepare(p);
336
337 pinctrl_pm_select_sleep_state(p->dev);
338
339 return 0;
340 }
341
max96772_panel_enable(struct drm_panel * panel)342 static int max96772_panel_enable(struct drm_panel *panel)
343 {
344 struct max96772_panel *p = to_max96772_panel(panel);
345
346 max96776_enable(p);
347
348 if (p->desc->enable)
349 p->desc->enable(p);
350
351 backlight_enable(p->backlight);
352
353 if (p->desc->backlight_enable)
354 p->desc->backlight_enable(p);
355
356 return 0;
357 }
358
max96772_panel_disable(struct drm_panel * panel)359 static int max96772_panel_disable(struct drm_panel *panel)
360 {
361 struct max96772_panel *p = to_max96772_panel(panel);
362
363 if (p->desc->backlight_disable)
364 p->desc->backlight_disable(p);
365
366 backlight_disable(p->backlight);
367
368 if (p->desc->disable)
369 p->desc->disable(p);
370
371 return 0;
372 }
373
max96772_panel_get_modes(struct drm_panel * panel,struct drm_connector * connector)374 static int max96772_panel_get_modes(struct drm_panel *panel,
375 struct drm_connector *connector)
376 {
377 struct max96772_panel *p = to_max96772_panel(panel);
378 struct drm_display_mode *mode;
379 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
380
381 connector->display_info.width_mm = p->desc->width_mm;
382 connector->display_info.height_mm = p->desc->height_mm;
383 drm_display_info_set_bus_formats(&connector->display_info, &bus_format, 1);
384
385 mode = drm_mode_duplicate(connector->dev, &p->mode);
386 mode->width_mm = p->desc->width_mm;
387 mode->height_mm = p->desc->height_mm;
388 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
389
390 drm_mode_set_name(mode);
391 drm_mode_probed_add(connector, mode);
392
393 return 1;
394 }
395
396 static const struct drm_panel_funcs max96772_panel_funcs = {
397 .prepare = max96772_panel_prepare,
398 .unprepare = max96772_panel_unprepare,
399 .enable = max96772_panel_enable,
400 .disable = max96772_panel_disable,
401 .get_modes = max96772_panel_get_modes,
402 };
403
max96772_panel_parse_dt(struct max96772_panel * p)404 static int max96772_panel_parse_dt(struct max96772_panel *p)
405 {
406 struct device *dev = p->dev;
407 struct display_timing dt;
408 struct videomode vm;
409 int ret;
410
411 ret = of_get_display_timing(dev->of_node, "panel-timing", &dt);
412 if (ret < 0) {
413 dev_err(dev, "%pOF: no panel-timing node found\n", dev->of_node);
414 return ret;
415 }
416
417 videomode_from_timing(&dt, &vm);
418 drm_display_mode_from_videomode(&vm, &p->mode);
419 p->panel_dual_link = of_property_read_bool(dev->of_node, "panel_dual_link");
420
421 return 0;
422 }
423
424 static const struct regmap_range max96772_readable_ranges[] = {
425 regmap_reg_range(0x0000, 0x0800),
426 regmap_reg_range(0x1700, 0x1700),
427 regmap_reg_range(0x4100, 0x4100),
428 regmap_reg_range(0x6230, 0x6230),
429 regmap_reg_range(0xe75e, 0xe75e),
430 regmap_reg_range(0xe776, 0xe7bf),
431 };
432
433 static const struct regmap_access_table max96772_readable_table = {
434 .yes_ranges = max96772_readable_ranges,
435 .n_yes_ranges = ARRAY_SIZE(max96772_readable_ranges),
436 };
437
438 static const struct regmap_config max96772_regmap_config = {
439 .name = "max96772",
440 .reg_bits = 16,
441 .val_bits = 8,
442 .max_register = 0xffff,
443 .rd_table = &max96772_readable_table,
444 };
445
max96772_panel_probe(struct i2c_client * client)446 static int max96772_panel_probe(struct i2c_client *client)
447 {
448 struct device *dev = &client->dev;
449 struct max96772_panel *p;
450 struct i2c_client *parent;
451 int ret;
452
453 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
454 if (!p)
455 return -ENOMEM;
456
457 p->dev = dev;
458 p->desc = of_device_get_match_data(dev);
459 i2c_set_clientdata(client, p);
460
461 ret = max96772_panel_parse_dt(p);
462 if (ret)
463 return dev_err_probe(dev, ret, "failed to parse DT\n");
464
465 p->backlight = devm_of_find_backlight(dev);
466 if (IS_ERR(p->backlight))
467 return dev_err_probe(dev, PTR_ERR(p->backlight),
468 "failed to get backlight\n");
469
470 p->regmap.deserializer =
471 devm_regmap_init_i2c(client, &max96772_regmap_config);
472 if (IS_ERR(p->regmap.deserializer))
473 return dev_err_probe(dev, PTR_ERR(p->regmap.deserializer),
474 "failed to initialize deserializer regmap\n");
475
476 parent = of_find_i2c_device_by_node(dev->of_node->parent->parent);
477 if (!parent)
478 return dev_err_probe(dev, -ENODEV, "failed to find parent\n");
479
480 p->regmap.serializer = dev_get_regmap(&parent->dev, NULL);
481 if (!p->regmap.serializer)
482 return dev_err_probe(dev, -ENODEV,
483 "failed to initialize serializer regmap\n");
484
485 drm_panel_init(&p->panel, dev, &max96772_panel_funcs,
486 DRM_MODE_CONNECTOR_eDP);
487 drm_panel_add(&p->panel);
488
489 return 0;
490 }
491
max96772_panel_remove(struct i2c_client * client)492 static int max96772_panel_remove(struct i2c_client *client)
493 {
494 struct max96772_panel *p = i2c_get_clientdata(client);
495
496 drm_panel_remove(&p->panel);
497
498 return 0;
499 }
500
boe_ae146m1t_l10_prepare(struct max96772_panel * p)501 static int boe_ae146m1t_l10_prepare(struct max96772_panel *p)
502 {
503 return 0;
504 }
505
boe_ae146m1t_l10_unprepare(struct max96772_panel * p)506 static int boe_ae146m1t_l10_unprepare(struct max96772_panel *p)
507 {
508 return 0;
509 }
510
511
512 static const struct panel_desc boe_ae146m1t_l10 = {
513 .name = "boe,ae146mit0-l10",
514 .width_mm = 323,
515 .height_mm = 182,
516 .link_rate = DP_LINK_BW_2_7,
517 .lane_count = 4,
518 .ssc = 0,
519 .prepare = boe_ae146m1t_l10_prepare,
520 .unprepare = boe_ae146m1t_l10_unprepare,
521
522 };
523
524 static const struct of_device_id max96772_panel_of_match[] = {
525 { .compatible = "boe,ae146m1t-l10", &boe_ae146m1t_l10 },
526 { }
527 };
528 MODULE_DEVICE_TABLE(of, max96772_panel_of_match);
529
530 static struct i2c_driver max96772_panel_driver = {
531 .driver = {
532 .name = "max96772-panel",
533 .of_match_table = max96772_panel_of_match,
534 },
535 .probe_new = max96772_panel_probe,
536 .remove = max96772_panel_remove,
537 };
538
539 module_i2c_driver(max96772_panel_driver);
540
541 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
542 MODULE_DESCRIPTION("Maxim MAX96772 based panel driver");
543 MODULE_LICENSE("GPL");
544