xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/parade-ps8622.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Parade PS8622 eDP/LVDS bridge driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2014 Google, Inc.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/backlight.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
12*4882a593Smuzhiyun #include <linux/i2c.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/of_device.h>
16*4882a593Smuzhiyun #include <linux/pm.h>
17*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_bridge.h>
21*4882a593Smuzhiyun #include <drm/drm_crtc.h>
22*4882a593Smuzhiyun #include <drm/drm_of.h>
23*4882a593Smuzhiyun #include <drm/drm_panel.h>
24*4882a593Smuzhiyun #include <drm/drm_print.h>
25*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* Brightness scale on the Parade chip */
28*4882a593Smuzhiyun #define PS8622_MAX_BRIGHTNESS 0xff
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /* Timings taken from the version 1.7 datasheet for the PS8622/PS8625 */
31*4882a593Smuzhiyun #define PS8622_POWER_RISE_T1_MIN_US 10
32*4882a593Smuzhiyun #define PS8622_POWER_RISE_T1_MAX_US 10000
33*4882a593Smuzhiyun #define PS8622_RST_HIGH_T2_MIN_US 3000
34*4882a593Smuzhiyun #define PS8622_RST_HIGH_T2_MAX_US 30000
35*4882a593Smuzhiyun #define PS8622_PWMO_END_T12_MS 200
36*4882a593Smuzhiyun #define PS8622_POWER_FALL_T16_MAX_US 10000
37*4882a593Smuzhiyun #define PS8622_POWER_OFF_T17_MS 500
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #if ((PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US) > \
40*4882a593Smuzhiyun 	(PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US))
41*4882a593Smuzhiyun #error "T2.min + T1.max must be less than T2.max + T1.min"
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun struct ps8622_bridge {
45*4882a593Smuzhiyun 	struct i2c_client *client;
46*4882a593Smuzhiyun 	struct drm_bridge bridge;
47*4882a593Smuzhiyun 	struct drm_bridge *panel_bridge;
48*4882a593Smuzhiyun 	struct regulator *v12;
49*4882a593Smuzhiyun 	struct backlight_device *bl;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	struct gpio_desc *gpio_slp;
52*4882a593Smuzhiyun 	struct gpio_desc *gpio_rst;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	u32 max_lane_count;
55*4882a593Smuzhiyun 	u32 lane_count;
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	bool enabled;
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun static inline struct ps8622_bridge *
bridge_to_ps8622(struct drm_bridge * bridge)61*4882a593Smuzhiyun 		bridge_to_ps8622(struct drm_bridge *bridge)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun 	return container_of(bridge, struct ps8622_bridge, bridge);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun 
ps8622_set(struct i2c_client * client,u8 page,u8 reg,u8 val)66*4882a593Smuzhiyun static int ps8622_set(struct i2c_client *client, u8 page, u8 reg, u8 val)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun 	int ret;
69*4882a593Smuzhiyun 	struct i2c_adapter *adap = client->adapter;
70*4882a593Smuzhiyun 	struct i2c_msg msg;
71*4882a593Smuzhiyun 	u8 data[] = {reg, val};
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	msg.addr = client->addr + page;
74*4882a593Smuzhiyun 	msg.flags = 0;
75*4882a593Smuzhiyun 	msg.len = sizeof(data);
76*4882a593Smuzhiyun 	msg.buf = data;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	ret = i2c_transfer(adap, &msg, 1);
79*4882a593Smuzhiyun 	if (ret != 1)
80*4882a593Smuzhiyun 		pr_warn("PS8622 I2C write (0x%02x,0x%02x,0x%02x) failed: %d\n",
81*4882a593Smuzhiyun 			client->addr + page, reg, val, ret);
82*4882a593Smuzhiyun 	return !(ret == 1);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun 
ps8622_send_config(struct ps8622_bridge * ps8622)85*4882a593Smuzhiyun static int ps8622_send_config(struct ps8622_bridge *ps8622)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun 	struct i2c_client *cl = ps8622->client;
88*4882a593Smuzhiyun 	int err = 0;
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun 	/* HPD low */
91*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x02, 0xa1, 0x01);
92*4882a593Smuzhiyun 	if (err)
93*4882a593Smuzhiyun 		goto error;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* SW setting: [1:0] SW output 1.2V voltage is lower to 96% */
96*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x14, 0x01);
97*4882a593Smuzhiyun 	if (err)
98*4882a593Smuzhiyun 		goto error;
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun 	/* RCO SS setting: [5:4] = b01 0.5%, b10 1%, b11 1.5% */
101*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0xe3, 0x20);
102*4882a593Smuzhiyun 	if (err)
103*4882a593Smuzhiyun 		goto error;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/* [7] RCO SS enable */
106*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0xe2, 0x80);
107*4882a593Smuzhiyun 	if (err)
108*4882a593Smuzhiyun 		goto error;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	/* RPHY Setting
111*4882a593Smuzhiyun 	 * [3:2] CDR tune wait cycle before measure for fine tune
112*4882a593Smuzhiyun 	 * b00: 1us b01: 0.5us b10:2us, b11: 4us
113*4882a593Smuzhiyun 	 */
114*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x8a, 0x0c);
115*4882a593Smuzhiyun 	if (err)
116*4882a593Smuzhiyun 		goto error;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	/* [3] RFD always on */
119*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x89, 0x08);
120*4882a593Smuzhiyun 	if (err)
121*4882a593Smuzhiyun 		goto error;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/* CTN lock in/out: 20000ppm/80000ppm. Lock out 2 times. */
124*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x71, 0x2d);
125*4882a593Smuzhiyun 	if (err)
126*4882a593Smuzhiyun 		goto error;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	/* 2.7G CDR settings: NOF=40LSB for HBR CDR  setting */
129*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x7d, 0x07);
130*4882a593Smuzhiyun 	if (err)
131*4882a593Smuzhiyun 		goto error;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	/* [1:0] Fmin=+4bands */
134*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x7b, 0x00);
135*4882a593Smuzhiyun 	if (err)
136*4882a593Smuzhiyun 		goto error;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/* [7:5] DCO_FTRNG=+-40% */
139*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x7a, 0xfd);
140*4882a593Smuzhiyun 	if (err)
141*4882a593Smuzhiyun 		goto error;
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun 	/* 1.62G CDR settings: [5:2]NOF=64LSB [1:0]DCO scale is 2/5 */
144*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0xc0, 0x12);
145*4882a593Smuzhiyun 	if (err)
146*4882a593Smuzhiyun 		goto error;
147*4882a593Smuzhiyun 
148*4882a593Smuzhiyun 	/* Gitune=-37% */
149*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0xc1, 0x92);
150*4882a593Smuzhiyun 	if (err)
151*4882a593Smuzhiyun 		goto error;
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	/* Fbstep=100% */
154*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0xc2, 0x1c);
155*4882a593Smuzhiyun 	if (err)
156*4882a593Smuzhiyun 		goto error;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* [7] LOS signal disable */
159*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x32, 0x80);
160*4882a593Smuzhiyun 	if (err)
161*4882a593Smuzhiyun 		goto error;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	/* RPIO Setting: [7:4] LVDS driver bias current : 75% (250mV swing) */
164*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x00, 0xb0);
165*4882a593Smuzhiyun 	if (err)
166*4882a593Smuzhiyun 		goto error;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	/* [7:6] Right-bar GPIO output strength is 8mA */
169*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x15, 0x40);
170*4882a593Smuzhiyun 	if (err)
171*4882a593Smuzhiyun 		goto error;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* EQ Training State Machine Setting, RCO calibration start */
174*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x54, 0x10);
175*4882a593Smuzhiyun 	if (err)
176*4882a593Smuzhiyun 		goto error;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/* Logic, needs more than 10 I2C command */
179*4882a593Smuzhiyun 	/* [4:0] MAX_LANE_COUNT set to max supported lanes */
180*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0x02, 0x80 | ps8622->max_lane_count);
181*4882a593Smuzhiyun 	if (err)
182*4882a593Smuzhiyun 		goto error;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	/* [4:0] LANE_COUNT_SET set to chosen lane count */
185*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count);
186*4882a593Smuzhiyun 	if (err)
187*4882a593Smuzhiyun 		goto error;
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0x52, 0x20);
190*4882a593Smuzhiyun 	if (err)
191*4882a593Smuzhiyun 		goto error;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* HPD CP toggle enable */
194*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0xf1, 0x03);
195*4882a593Smuzhiyun 	if (err)
196*4882a593Smuzhiyun 		goto error;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0x62, 0x41);
199*4882a593Smuzhiyun 	if (err)
200*4882a593Smuzhiyun 		goto error;
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	/* Counter number, add 1ms counter delay */
203*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0xf6, 0x01);
204*4882a593Smuzhiyun 	if (err)
205*4882a593Smuzhiyun 		goto error;
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	/* [6]PWM function control by DPCD0040f[7], default is PWM block */
208*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0x77, 0x06);
209*4882a593Smuzhiyun 	if (err)
210*4882a593Smuzhiyun 		goto error;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* 04h Adjust VTotal toleranceto fix the 30Hz no display issue */
213*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x00, 0x4c, 0x04);
214*4882a593Smuzhiyun 	if (err)
215*4882a593Smuzhiyun 		goto error;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	/* DPCD00400='h00, Parade OUI ='h001cf8 */
218*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc0, 0x00);
219*4882a593Smuzhiyun 	if (err)
220*4882a593Smuzhiyun 		goto error;
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	/* DPCD00401='h1c */
223*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc1, 0x1c);
224*4882a593Smuzhiyun 	if (err)
225*4882a593Smuzhiyun 		goto error;
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun 	/* DPCD00402='hf8 */
228*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc2, 0xf8);
229*4882a593Smuzhiyun 	if (err)
230*4882a593Smuzhiyun 		goto error;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	/* DPCD403~408 = ASCII code, D2SLV5='h4432534c5635 */
233*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc3, 0x44);
234*4882a593Smuzhiyun 	if (err)
235*4882a593Smuzhiyun 		goto error;
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/* DPCD404 */
238*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc4, 0x32);
239*4882a593Smuzhiyun 	if (err)
240*4882a593Smuzhiyun 		goto error;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	/* DPCD405 */
243*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc5, 0x53);
244*4882a593Smuzhiyun 	if (err)
245*4882a593Smuzhiyun 		goto error;
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun 	/* DPCD406 */
248*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc6, 0x4c);
249*4882a593Smuzhiyun 	if (err)
250*4882a593Smuzhiyun 		goto error;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* DPCD407 */
253*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc7, 0x56);
254*4882a593Smuzhiyun 	if (err)
255*4882a593Smuzhiyun 		goto error;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/* DPCD408 */
258*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xc8, 0x35);
259*4882a593Smuzhiyun 	if (err)
260*4882a593Smuzhiyun 		goto error;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* DPCD40A, Initial Code major revision '01' */
263*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xca, 0x01);
264*4882a593Smuzhiyun 	if (err)
265*4882a593Smuzhiyun 		goto error;
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	/* DPCD40B, Initial Code minor revision '05' */
268*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xcb, 0x05);
269*4882a593Smuzhiyun 	if (err)
270*4882a593Smuzhiyun 		goto error;
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	if (ps8622->bl) {
274*4882a593Smuzhiyun 		/* DPCD720, internal PWM */
275*4882a593Smuzhiyun 		err = ps8622_set(cl, 0x01, 0xa5, 0xa0);
276*4882a593Smuzhiyun 		if (err)
277*4882a593Smuzhiyun 			goto error;
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 		/* FFh for 100% brightness, 0h for 0% brightness */
280*4882a593Smuzhiyun 		err = ps8622_set(cl, 0x01, 0xa7,
281*4882a593Smuzhiyun 				ps8622->bl->props.brightness);
282*4882a593Smuzhiyun 		if (err)
283*4882a593Smuzhiyun 			goto error;
284*4882a593Smuzhiyun 	} else {
285*4882a593Smuzhiyun 		/* DPCD720, external PWM */
286*4882a593Smuzhiyun 		err = ps8622_set(cl, 0x01, 0xa5, 0x80);
287*4882a593Smuzhiyun 		if (err)
288*4882a593Smuzhiyun 			goto error;
289*4882a593Smuzhiyun 	}
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	/* Set LVDS output as 6bit-VESA mapping, single LVDS channel */
292*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x01, 0xcc, 0x13);
293*4882a593Smuzhiyun 	if (err)
294*4882a593Smuzhiyun 		goto error;
295*4882a593Smuzhiyun 
296*4882a593Smuzhiyun 	/* Enable SSC set by register */
297*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x02, 0xb1, 0x20);
298*4882a593Smuzhiyun 	if (err)
299*4882a593Smuzhiyun 		goto error;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	/* Set SSC enabled and +/-1% central spreading */
302*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x10, 0x16);
303*4882a593Smuzhiyun 	if (err)
304*4882a593Smuzhiyun 		goto error;
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun 	/* Logic end */
307*4882a593Smuzhiyun 	/* MPU Clock source: LC => RCO */
308*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x59, 0x60);
309*4882a593Smuzhiyun 	if (err)
310*4882a593Smuzhiyun 		goto error;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	/* LC -> RCO */
313*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x04, 0x54, 0x14);
314*4882a593Smuzhiyun 	if (err)
315*4882a593Smuzhiyun 		goto error;
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/* HPD high */
318*4882a593Smuzhiyun 	err = ps8622_set(cl, 0x02, 0xa1, 0x91);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun error:
321*4882a593Smuzhiyun 	return err ? -EIO : 0;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
ps8622_backlight_update(struct backlight_device * bl)324*4882a593Smuzhiyun static int ps8622_backlight_update(struct backlight_device *bl)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622 = dev_get_drvdata(&bl->dev);
327*4882a593Smuzhiyun 	int ret, brightness = bl->props.brightness;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	if (bl->props.power != FB_BLANK_UNBLANK ||
330*4882a593Smuzhiyun 	    bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
331*4882a593Smuzhiyun 		brightness = 0;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 	if (!ps8622->enabled)
334*4882a593Smuzhiyun 		return -EINVAL;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	ret = ps8622_set(ps8622->client, 0x01, 0xa7, brightness);
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	return ret;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun 
341*4882a593Smuzhiyun static const struct backlight_ops ps8622_backlight_ops = {
342*4882a593Smuzhiyun 	.update_status	= ps8622_backlight_update,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
ps8622_pre_enable(struct drm_bridge * bridge)345*4882a593Smuzhiyun static void ps8622_pre_enable(struct drm_bridge *bridge)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
348*4882a593Smuzhiyun 	int ret;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	if (ps8622->enabled)
351*4882a593Smuzhiyun 		return;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	gpiod_set_value(ps8622->gpio_rst, 0);
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	if (ps8622->v12) {
356*4882a593Smuzhiyun 		ret = regulator_enable(ps8622->v12);
357*4882a593Smuzhiyun 		if (ret)
358*4882a593Smuzhiyun 			DRM_ERROR("fails to enable ps8622->v12");
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	gpiod_set_value(ps8622->gpio_slp, 1);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	/*
364*4882a593Smuzhiyun 	 * T1 is the range of time that it takes for the power to rise after we
365*4882a593Smuzhiyun 	 * enable the lcd/ps8622 fet. T2 is the range of time in which the
366*4882a593Smuzhiyun 	 * data sheet specifies we should deassert the reset pin.
367*4882a593Smuzhiyun 	 *
368*4882a593Smuzhiyun 	 * If it takes T1.max for the power to rise, we need to wait atleast
369*4882a593Smuzhiyun 	 * T2.min before deasserting the reset pin. If it takes T1.min for the
370*4882a593Smuzhiyun 	 * power to rise, we need to wait at most T2.max before deasserting the
371*4882a593Smuzhiyun 	 * reset pin.
372*4882a593Smuzhiyun 	 */
373*4882a593Smuzhiyun 	usleep_range(PS8622_RST_HIGH_T2_MIN_US + PS8622_POWER_RISE_T1_MAX_US,
374*4882a593Smuzhiyun 		     PS8622_RST_HIGH_T2_MAX_US + PS8622_POWER_RISE_T1_MIN_US);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	gpiod_set_value(ps8622->gpio_rst, 1);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	/* wait 20ms after RST high */
379*4882a593Smuzhiyun 	usleep_range(20000, 30000);
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun 	ret = ps8622_send_config(ps8622);
382*4882a593Smuzhiyun 	if (ret) {
383*4882a593Smuzhiyun 		DRM_ERROR("Failed to send config to bridge (%d)\n", ret);
384*4882a593Smuzhiyun 		return;
385*4882a593Smuzhiyun 	}
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	ps8622->enabled = true;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
ps8622_disable(struct drm_bridge * bridge)390*4882a593Smuzhiyun static void ps8622_disable(struct drm_bridge *bridge)
391*4882a593Smuzhiyun {
392*4882a593Smuzhiyun 	/* Delay after panel is disabled */
393*4882a593Smuzhiyun 	msleep(PS8622_PWMO_END_T12_MS);
394*4882a593Smuzhiyun }
395*4882a593Smuzhiyun 
ps8622_post_disable(struct drm_bridge * bridge)396*4882a593Smuzhiyun static void ps8622_post_disable(struct drm_bridge *bridge)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	if (!ps8622->enabled)
401*4882a593Smuzhiyun 		return;
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun 	ps8622->enabled = false;
404*4882a593Smuzhiyun 
405*4882a593Smuzhiyun 	/*
406*4882a593Smuzhiyun 	 * This doesn't matter if the regulators are turned off, but something
407*4882a593Smuzhiyun 	 * else might keep them on. In that case, we want to assert the slp gpio
408*4882a593Smuzhiyun 	 * to lower power.
409*4882a593Smuzhiyun 	 */
410*4882a593Smuzhiyun 	gpiod_set_value(ps8622->gpio_slp, 0);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	if (ps8622->v12)
413*4882a593Smuzhiyun 		regulator_disable(ps8622->v12);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	/*
416*4882a593Smuzhiyun 	 * Sleep for at least the amount of time that it takes the power rail to
417*4882a593Smuzhiyun 	 * fall to prevent asserting the rst gpio from doing anything.
418*4882a593Smuzhiyun 	 */
419*4882a593Smuzhiyun 	usleep_range(PS8622_POWER_FALL_T16_MAX_US,
420*4882a593Smuzhiyun 		     2 * PS8622_POWER_FALL_T16_MAX_US);
421*4882a593Smuzhiyun 	gpiod_set_value(ps8622->gpio_rst, 0);
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	msleep(PS8622_POWER_OFF_T17_MS);
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun 
ps8622_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)426*4882a593Smuzhiyun static int ps8622_attach(struct drm_bridge *bridge,
427*4882a593Smuzhiyun 			 enum drm_bridge_attach_flags flags)
428*4882a593Smuzhiyun {
429*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622 = bridge_to_ps8622(bridge);
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	return drm_bridge_attach(ps8622->bridge.encoder, ps8622->panel_bridge,
432*4882a593Smuzhiyun 				 &ps8622->bridge, flags);
433*4882a593Smuzhiyun }
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun static const struct drm_bridge_funcs ps8622_bridge_funcs = {
436*4882a593Smuzhiyun 	.pre_enable = ps8622_pre_enable,
437*4882a593Smuzhiyun 	.disable = ps8622_disable,
438*4882a593Smuzhiyun 	.post_disable = ps8622_post_disable,
439*4882a593Smuzhiyun 	.attach = ps8622_attach,
440*4882a593Smuzhiyun };
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun static const struct of_device_id ps8622_devices[] = {
443*4882a593Smuzhiyun 	{.compatible = "parade,ps8622",},
444*4882a593Smuzhiyun 	{.compatible = "parade,ps8625",},
445*4882a593Smuzhiyun 	{}
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ps8622_devices);
448*4882a593Smuzhiyun 
ps8622_probe(struct i2c_client * client,const struct i2c_device_id * id)449*4882a593Smuzhiyun static int ps8622_probe(struct i2c_client *client,
450*4882a593Smuzhiyun 					const struct i2c_device_id *id)
451*4882a593Smuzhiyun {
452*4882a593Smuzhiyun 	struct device *dev = &client->dev;
453*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622;
454*4882a593Smuzhiyun 	struct drm_bridge *panel_bridge;
455*4882a593Smuzhiyun 	struct drm_panel *panel;
456*4882a593Smuzhiyun 	int ret;
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun 	ps8622 = devm_kzalloc(dev, sizeof(*ps8622), GFP_KERNEL);
459*4882a593Smuzhiyun 	if (!ps8622)
460*4882a593Smuzhiyun 		return -ENOMEM;
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0, &panel, NULL);
463*4882a593Smuzhiyun 	if (ret)
464*4882a593Smuzhiyun 		return ret;
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun 	panel_bridge = devm_drm_panel_bridge_add(dev, panel);
467*4882a593Smuzhiyun 	if (IS_ERR(panel_bridge))
468*4882a593Smuzhiyun 		return PTR_ERR(panel_bridge);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	ps8622->panel_bridge = panel_bridge;
471*4882a593Smuzhiyun 	ps8622->client = client;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	ps8622->v12 = devm_regulator_get(dev, "vdd12");
474*4882a593Smuzhiyun 	if (IS_ERR(ps8622->v12)) {
475*4882a593Smuzhiyun 		dev_info(dev, "no 1.2v regulator found for PS8622\n");
476*4882a593Smuzhiyun 		ps8622->v12 = NULL;
477*4882a593Smuzhiyun 	}
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	ps8622->gpio_slp = devm_gpiod_get(dev, "sleep", GPIOD_OUT_HIGH);
480*4882a593Smuzhiyun 	if (IS_ERR(ps8622->gpio_slp)) {
481*4882a593Smuzhiyun 		ret = PTR_ERR(ps8622->gpio_slp);
482*4882a593Smuzhiyun 		dev_err(dev, "cannot get gpio_slp %d\n", ret);
483*4882a593Smuzhiyun 		return ret;
484*4882a593Smuzhiyun 	}
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	/*
487*4882a593Smuzhiyun 	 * Assert the reset pin high to avoid the bridge being
488*4882a593Smuzhiyun 	 * initialized prematurely
489*4882a593Smuzhiyun 	 */
490*4882a593Smuzhiyun 	ps8622->gpio_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
491*4882a593Smuzhiyun 	if (IS_ERR(ps8622->gpio_rst)) {
492*4882a593Smuzhiyun 		ret = PTR_ERR(ps8622->gpio_rst);
493*4882a593Smuzhiyun 		dev_err(dev, "cannot get gpio_rst %d\n", ret);
494*4882a593Smuzhiyun 		return ret;
495*4882a593Smuzhiyun 	}
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 	ps8622->max_lane_count = id->driver_data;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	if (of_property_read_u32(dev->of_node, "lane-count",
500*4882a593Smuzhiyun 						&ps8622->lane_count)) {
501*4882a593Smuzhiyun 		ps8622->lane_count = ps8622->max_lane_count;
502*4882a593Smuzhiyun 	} else if (ps8622->lane_count > ps8622->max_lane_count) {
503*4882a593Smuzhiyun 		dev_info(dev, "lane-count property is too high,"
504*4882a593Smuzhiyun 						"using max_lane_count\n");
505*4882a593Smuzhiyun 		ps8622->lane_count = ps8622->max_lane_count;
506*4882a593Smuzhiyun 	}
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	if (!of_find_property(dev->of_node, "use-external-pwm", NULL)) {
509*4882a593Smuzhiyun 		ps8622->bl = backlight_device_register("ps8622-backlight",
510*4882a593Smuzhiyun 				dev, ps8622, &ps8622_backlight_ops,
511*4882a593Smuzhiyun 				NULL);
512*4882a593Smuzhiyun 		if (IS_ERR(ps8622->bl)) {
513*4882a593Smuzhiyun 			DRM_ERROR("failed to register backlight\n");
514*4882a593Smuzhiyun 			ret = PTR_ERR(ps8622->bl);
515*4882a593Smuzhiyun 			ps8622->bl = NULL;
516*4882a593Smuzhiyun 			return ret;
517*4882a593Smuzhiyun 		}
518*4882a593Smuzhiyun 		ps8622->bl->props.max_brightness = PS8622_MAX_BRIGHTNESS;
519*4882a593Smuzhiyun 		ps8622->bl->props.brightness = PS8622_MAX_BRIGHTNESS;
520*4882a593Smuzhiyun 	}
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	ps8622->bridge.funcs = &ps8622_bridge_funcs;
523*4882a593Smuzhiyun 	ps8622->bridge.type = DRM_MODE_CONNECTOR_LVDS;
524*4882a593Smuzhiyun 	ps8622->bridge.of_node = dev->of_node;
525*4882a593Smuzhiyun 	drm_bridge_add(&ps8622->bridge);
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun 	i2c_set_clientdata(client, ps8622);
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	return 0;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun 
ps8622_remove(struct i2c_client * client)532*4882a593Smuzhiyun static int ps8622_remove(struct i2c_client *client)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun 	struct ps8622_bridge *ps8622 = i2c_get_clientdata(client);
535*4882a593Smuzhiyun 
536*4882a593Smuzhiyun 	backlight_device_unregister(ps8622->bl);
537*4882a593Smuzhiyun 	drm_bridge_remove(&ps8622->bridge);
538*4882a593Smuzhiyun 
539*4882a593Smuzhiyun 	return 0;
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun static const struct i2c_device_id ps8622_i2c_table[] = {
543*4882a593Smuzhiyun 	/* Device type, max_lane_count */
544*4882a593Smuzhiyun 	{"ps8622", 1},
545*4882a593Smuzhiyun 	{"ps8625", 2},
546*4882a593Smuzhiyun 	{},
547*4882a593Smuzhiyun };
548*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, ps8622_i2c_table);
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun static struct i2c_driver ps8622_driver = {
551*4882a593Smuzhiyun 	.id_table	= ps8622_i2c_table,
552*4882a593Smuzhiyun 	.probe		= ps8622_probe,
553*4882a593Smuzhiyun 	.remove		= ps8622_remove,
554*4882a593Smuzhiyun 	.driver		= {
555*4882a593Smuzhiyun 		.name	= "ps8622",
556*4882a593Smuzhiyun 		.of_match_table = ps8622_devices,
557*4882a593Smuzhiyun 	},
558*4882a593Smuzhiyun };
559*4882a593Smuzhiyun module_i2c_driver(ps8622_driver);
560*4882a593Smuzhiyun 
561*4882a593Smuzhiyun MODULE_AUTHOR("Vincent Palatin <vpalatin@chromium.org>");
562*4882a593Smuzhiyun MODULE_DESCRIPTION("Parade ps8622/ps8625 eDP-LVDS converter driver");
563*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
564