1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __INTEL_DP_H__
7*4882a593Smuzhiyun #define __INTEL_DP_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/types.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include "i915_reg.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun enum pipe;
14*4882a593Smuzhiyun enum port;
15*4882a593Smuzhiyun struct drm_connector_state;
16*4882a593Smuzhiyun struct drm_encoder;
17*4882a593Smuzhiyun struct drm_i915_private;
18*4882a593Smuzhiyun struct drm_modeset_acquire_ctx;
19*4882a593Smuzhiyun struct drm_dp_vsc_sdp;
20*4882a593Smuzhiyun struct intel_atomic_state;
21*4882a593Smuzhiyun struct intel_connector;
22*4882a593Smuzhiyun struct intel_crtc_state;
23*4882a593Smuzhiyun struct intel_digital_port;
24*4882a593Smuzhiyun struct intel_dp;
25*4882a593Smuzhiyun struct intel_encoder;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct link_config_limits {
28*4882a593Smuzhiyun int min_clock, max_clock;
29*4882a593Smuzhiyun int min_lane_count, max_lane_count;
30*4882a593Smuzhiyun int min_bpp, max_bpp;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
34*4882a593Smuzhiyun struct intel_crtc_state *pipe_config,
35*4882a593Smuzhiyun struct link_config_limits *limits);
36*4882a593Smuzhiyun bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
37*4882a593Smuzhiyun const struct drm_connector_state *conn_state);
38*4882a593Smuzhiyun int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
39*4882a593Smuzhiyun bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
40*4882a593Smuzhiyun i915_reg_t dp_reg, enum port port,
41*4882a593Smuzhiyun enum pipe *pipe);
42*4882a593Smuzhiyun bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
43*4882a593Smuzhiyun enum port port);
44*4882a593Smuzhiyun bool intel_dp_init_connector(struct intel_digital_port *dig_port,
45*4882a593Smuzhiyun struct intel_connector *intel_connector);
46*4882a593Smuzhiyun void intel_dp_set_link_params(struct intel_dp *intel_dp,
47*4882a593Smuzhiyun int link_rate, u8 lane_count,
48*4882a593Smuzhiyun bool link_mst);
49*4882a593Smuzhiyun int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
50*4882a593Smuzhiyun int link_rate, u8 lane_count);
51*4882a593Smuzhiyun int intel_dp_retrain_link(struct intel_encoder *encoder,
52*4882a593Smuzhiyun struct drm_modeset_acquire_ctx *ctx);
53*4882a593Smuzhiyun void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode);
54*4882a593Smuzhiyun void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,
55*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state);
56*4882a593Smuzhiyun void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
57*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
58*4882a593Smuzhiyun bool enable);
59*4882a593Smuzhiyun void intel_dp_encoder_reset(struct drm_encoder *encoder);
60*4882a593Smuzhiyun void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
61*4882a593Smuzhiyun void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
62*4882a593Smuzhiyun int intel_dp_compute_config(struct intel_encoder *encoder,
63*4882a593Smuzhiyun struct intel_crtc_state *pipe_config,
64*4882a593Smuzhiyun struct drm_connector_state *conn_state);
65*4882a593Smuzhiyun bool intel_dp_is_edp(struct intel_dp *intel_dp);
66*4882a593Smuzhiyun bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
67*4882a593Smuzhiyun enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *dig_port,
68*4882a593Smuzhiyun bool long_hpd);
69*4882a593Smuzhiyun void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
70*4882a593Smuzhiyun const struct drm_connector_state *conn_state);
71*4882a593Smuzhiyun void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
72*4882a593Smuzhiyun void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
73*4882a593Smuzhiyun void intel_edp_panel_on(struct intel_dp *intel_dp);
74*4882a593Smuzhiyun void intel_edp_panel_off(struct intel_dp *intel_dp);
75*4882a593Smuzhiyun void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
76*4882a593Smuzhiyun void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
77*4882a593Smuzhiyun int intel_dp_max_link_rate(struct intel_dp *intel_dp);
78*4882a593Smuzhiyun int intel_dp_max_lane_count(struct intel_dp *intel_dp);
79*4882a593Smuzhiyun int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
80*4882a593Smuzhiyun void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
81*4882a593Smuzhiyun u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun void intel_edp_drrs_enable(struct intel_dp *intel_dp,
84*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state);
85*4882a593Smuzhiyun void intel_edp_drrs_disable(struct intel_dp *intel_dp,
86*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state);
87*4882a593Smuzhiyun void intel_edp_drrs_update(struct intel_dp *intel_dp,
88*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state);
89*4882a593Smuzhiyun void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
90*4882a593Smuzhiyun unsigned int frontbuffer_bits);
91*4882a593Smuzhiyun void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
92*4882a593Smuzhiyun unsigned int frontbuffer_bits);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun void
95*4882a593Smuzhiyun intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
96*4882a593Smuzhiyun u8 dp_train_pat);
97*4882a593Smuzhiyun void
98*4882a593Smuzhiyun intel_dp_set_signal_levels(struct intel_dp *intel_dp);
99*4882a593Smuzhiyun void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
100*4882a593Smuzhiyun void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
101*4882a593Smuzhiyun u8 *link_bw, u8 *rate_select);
102*4882a593Smuzhiyun bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
103*4882a593Smuzhiyun bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
104*4882a593Smuzhiyun bool
105*4882a593Smuzhiyun intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
108*4882a593Smuzhiyun int intel_dp_link_required(int pixel_clock, int bpp);
109*4882a593Smuzhiyun int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
110*4882a593Smuzhiyun bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
111*4882a593Smuzhiyun const struct drm_connector_state *conn_state);
112*4882a593Smuzhiyun void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
113*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
114*4882a593Smuzhiyun const struct drm_connector_state *conn_state,
115*4882a593Smuzhiyun struct drm_dp_vsc_sdp *vsc);
116*4882a593Smuzhiyun void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
117*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
118*4882a593Smuzhiyun struct drm_dp_vsc_sdp *vsc);
119*4882a593Smuzhiyun void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
120*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
121*4882a593Smuzhiyun const struct drm_connector_state *conn_state);
122*4882a593Smuzhiyun void intel_read_dp_sdp(struct intel_encoder *encoder,
123*4882a593Smuzhiyun struct intel_crtc_state *crtc_state,
124*4882a593Smuzhiyun unsigned int type);
125*4882a593Smuzhiyun bool intel_digital_port_connected(struct intel_encoder *encoder);
126*4882a593Smuzhiyun void intel_dp_process_phy_request(struct intel_dp *intel_dp);
127*4882a593Smuzhiyun
intel_dp_unused_lane_mask(int lane_count)128*4882a593Smuzhiyun static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun return ~((1 << lane_count) - 1) & 0xf;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun void intel_ddi_update_pipe(struct intel_atomic_state *state,
136*4882a593Smuzhiyun struct intel_encoder *encoder,
137*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state,
138*4882a593Smuzhiyun const struct drm_connector_state *conn_state);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun int intel_dp_init_hdcp(struct intel_digital_port *dig_port,
141*4882a593Smuzhiyun struct intel_connector *intel_connector);
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #endif /* __INTEL_DP_H__ */
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