| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_image_load.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| H A D | socfpga_delay_timer.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/n5x/include/ |
| H A D | n5x_clock_manager.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| H A D | socfpga_plat_def.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_pinmux.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_power_manager.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| H A D | socfpga_plat_def.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex5/ |
| H A D | bl31_plat_setup.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| H A D | bl2_plat_setup.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/common/soc/ |
| H A D | socfpga_reset_manager.c | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/stratix10/include/ |
| H A D | socfpga_plat_def.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | socfpga_plat_def.h | b3d28508427225f41d55fa3b10fe4f1f1dfbd238 Mon Aug 26 16:01:51 UTC 2024 Sieu Mun Tang <sieu.mun.tang@intel.com> fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
|