| #
39850944 |
| 16-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration
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| #
b3d28508 |
| 26-Aug-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u
fix(intel): update Agilex5 BL2 init flow and other misc changes
BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates
Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
9118bdf4 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
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| #
150d2be0 |
| 07-Jul-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06a
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
ffc56bd0 |
| 17-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes I43a9d83c,Ibfaa47fb into integration
* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X
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| #
02a9d70c |
| 23-Jun-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signe
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed
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| #
aa69de86 |
| 13-May-2022 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
* changes:
fix(intel): remove unused printout
fix(intel): fix configuration status based on start request
style(intel): a
Merge changes I50721040,I1ce4b7b4,I9658aef7,I40ff55eb into integration
* changes:
fix(intel): remove unused printout
fix(intel): fix configuration status based on start request
style(intel): align the sequence in header file
fix(intel): remove redundant NOC header declarations
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| #
0d19eda0 |
| 13-May-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): remove unused printout
This patch is to remove unused printout.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I507210402dcbaf8369209308ae1fcedaccb0292d
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| #
026dfed8 |
| 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(intel): implement timer init divider via cpu frequency. (#1)" into integration
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| #
f65bdf3a |
| 06-Apr-2022 |
BenjaminLimJL <jit.loon.lim@intel.com> |
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The impl
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
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| #
141568da |
| 08-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agile
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agilex
plat: intel: Add FPGAINTF configuration to when configuring pinmux
plat: intel: set DRVSEL and SMPLSEL for DWMMC
plat: intel: Fix clock configuration bugs
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| #
811af8b7 |
| 11-May-2020 |
Tien Hock Loh <tien.hock.loh@intel.com> |
plat: intel: Additional instruction required to enable global timer
There are additional instruction needed to enable the global timer.
This fixes the global timer initialization
Signed-off-by: Tie
plat: intel: Additional instruction required to enable global timer
There are additional instruction needed to enable the global timer.
This fixes the global timer initialization
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Idaf2d23359aacc417e2b7d8cdf1688b5cd17ca98
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| #
5119fa7b |
| 07-Aug-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "intel-plat-refactor" into integration
* changes:
intel: Platform common code refactor
intel: Platform common code refactor
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| #
d8820789 |
| 01-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Platform common code refactor
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5
intel: Platform common code refactor
Pull out common code from agilex and stratix10
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Iddc0a9e6eccb30823d7b15615d5ce9c6bedb2abc
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