Merge "fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang" into integration

fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang

On FP82, performing FPGA configuration in U-Boot followed by a
second configuration in Linux via devicetree overlay can lead
to a s

fix(intel): add 5us delay before Linux reconfig to avoid HNOC hang

On FP82, performing FPGA configuration in U-Boot followed by a
second configuration in Linux via devicetree overlay can lead
to a system hang. This issue does not occur on Agilex or Agilex5.

Root cause is tied to FP82's HNOC (Hardened Network-on-Chip),
which requires a brief settling period after bridge enablement
and initial fabric reconfiguration. Without this delay, HNOC
may still be transitioning, resulting in unstable FPGA access.

A 5us delay is added before the Linux reconfiguration step
to ensure HNOC is fully stabilized. Verified on FP82. No impact
on other platforms.

Change-Id: I083d395d34c797c4bf0a7e8aadc7c8866661fc15
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge "fix(intel): update debug messages to appropriate class" into integration

fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <g

fix(intel): update debug messages to appropriate class

Update debug messages to VERBOSE class wherever required.

Change-Id: I44ea6b660581285290f54a507dd1131d26be2ec8
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>

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Merge changes I52c84dc2,I9b2a2a11 into integration

* changes:
fix(intel): add FPGA isolation trigger when reconfiguration
fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-of

fix(intel): redesign F2SOC bridge enable and disable flow for Agilex5

This is to redesign the flow of F2SOC bridge enable and disable.

Change-Id: I9b2a2a11fa2ad8e622765971fdf59a0738246e13
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): implement soc and lwsoc bridge control for burst speed" into integration

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90

fix(intel): implement soc and lwsoc bridge control for burst speed

Implement burst speed read/write for SOC and LWSOC. Set bridge control
register to enable the register bit

Change-Id: I815b912cb90d79a548163d198eea177d70dfbc0d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): fix bridge enable and disable function" into integration

Merge "fix(intel): update outdated code for Linux direct boot" into integration

Merge "fix(intel): update Agilex5 BL2 init flow and other misc changes" into integration

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4. bridge timeout workaround for F2SOC and F2SDRAM


Change-Id: Ide4210ff862531f82e083633af385b559ffbe16b
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df

fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc u

fix(intel): update Agilex5 BL2 init flow and other misc changes

BL2: Update BL2 init flow, Timer base address, avoid cache
flush of BL2 image descriptors
BL31: Remove re-init of CCU and other misc updates

Change-Id: I5f04901cc455c306209c83aad2377bbf7d8a1789
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "fix(intel): bridge ack timing issue causing fpga config hung" into integration

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signe

fix(intel): bridge ack timing issue causing fpga config hung

Increase the timeout of waiting for bridge ack to solve the
fpga config hung.

Change-Id: I967af02b336c296206b4947be718953ff8ca30cf
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): software workaround for bridge timeout" into integration

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id

fix(intel): software workaround for bridge timeout

Hardware hdskack register does not return a correct value after
fence and drain of the bridge is done. Thus creates software
workaround.

Change-Id: I78d8ee0596c3e7bd4883bfd6e92c883b8e369c10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): f2sdram bridge quick write thru failed" into integration

fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb

fix(intel): f2sdram bridge quick write thru failed

This patch is to fix the f2sdram bridge quick write thru failing by
removing the clear bit for sidebandmgr flagout register.

Change-Id: Ib03498fbb2d91e9fd85f6315091ff72cbe3f394d
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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Merge "fix(intel): update from INFO to VERBOSE when print debug message" into integration

fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44

fix(intel): update from INFO to VERBOSE when print debug message

Update from INFO to VERBOSE when print out debug message.

Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Iefdbd44e711c0fd589bef454b42754cf9e3cd391

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Merge "fix(intel): update HPS bridges for Agilex5 SoC FPGA" into integration

Merge "fix(intel): update individual return result for hps and fpga bridges" into integration

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when

fix(intel): update individual return result for hps and fpga bridges

The code is designed to execute SOC2FPGA and LWSOC2FPGA first
then to F2SOC and both sharing the same result "return".
Thus when F2SOC is executed, the "return" result will overwrite
SOC2FPGA "return" result even though it is not enabled.
Using 2 different "return" result to for each bridges and
return both of them at the end of the function to
avoid being overwritten.

Change-Id: Id9de3f416fe3020db35bc946135b175be2a7dc1e
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

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