Searched +full:sun8i +full:- +full:a23 +full:- +full:prcm (Results 1 – 16 of 16) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.0+3 ---4 $id: http://devicetree.org/schemas/mfd/allwinner,sun8i-a23-prcm.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A23 PRCM Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>17 const: allwinner,sun8i-a23-prcm29 - fixed-factor-clock30 - allwinner,sun8i-a23-apb0-clk[all …]
1 // SPDX-License-Identifier: GPL-2.0-only5 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com>7 * Allwinner PRCM (Power/Reset/Clock Management) driver68 .name = "sun6i-a31-ar100-clk",69 .of_compatible = "allwinner,sun6i-a31-ar100-clk",74 .name = "sun6i-a31-apb0-clk",75 .of_compatible = "allwinner,sun6i-a31-apb0-clk",80 .name = "sun6i-a31-apb0-gates-clk",81 .of_compatible = "allwinner,sun6i-a31-apb0-gates-clk",86 .name = "sun6i-a31-ir-clk",[all …]
6 * Maxime Ripard <maxime.ripard@free-electrons.com>9 * Copyright (C) 2012-2013 Allwinner Ltd.46 node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm"); in sun6i_smp_prepare_cpus()48 pr_err("Missing A31 PRCM node in the device tree\n"); in sun6i_smp_prepare_cpus()55 pr_err("Couldn't map A31 PRCM registers\n"); in sun6i_smp_prepare_cpus()60 "allwinner,sun6i-a31-cpuconfig"); in sun6i_smp_prepare_cpus()80 return -EFAULT; in sun6i_smp_boot_secondary()104 /* Clear CPU power-off gating */ in sun6i_smp_boot_secondary()125 CPU_METHOD_OF_DECLARE(sun6i_a31_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);131 node = of_find_compatible_node(NULL, NULL, "allwinner,sun8i-a23-prcm"); in sun8i_smp_prepare_cpus()[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/sound/allwinner,sun8i-a23-codec-analog.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Allwinner A23 Analog Codec Device Tree Bindings10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>16 # FIXME: This is documented in the PRCM binding, but needs to be18 # - allwinner,sun8i-a23-codec-analog19 - allwinner,sun8i-h3-codec-analog[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/sound/allwinner,sun4i-a10-codec.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>14 "#sound-dai-cells":19 - allwinner,sun4i-a10-codec20 - allwinner,sun6i-a31-codec21 - allwinner,sun7i-a20-codec[all …]
1 # SPDX-License-Identifier: GPL-2.0-only14 A23, A31, A80) SoCs. These drivers are kept around for21 bool "Legacy A31 PRCM driver"25 Legacy clock driver for the A31 PRCM clocks. Those are29 bool "Legacy sun8i PRCM driver"33 Legacy clock driver for the sun8i family PRCM clocks.38 bool "Legacy A80 PRCM driver"41 Legacy clock driver for the A80 PRCM clocks. Those are
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/pinctrl/sun4i-a10.h>52 interrupt-parent = <&gic>;55 #address-cells = <1>;56 #size-cells = <1>;60 compatible = "allwinner,simple-framebuffer",61 "simple-framebuffer";[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms47 #include <dt-bindings/interrupt-controller/arm-gic.h>49 #include <dt-bindings/pinctrl/sun4i-a10.h>52 interrupt-parent = <&gic>;55 #address-cells = <1>;56 #size-cells = <0>;59 compatible = "arm,cortex-a7";65 compatible = "arm,cortex-a7";[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Chen-Yu Tsai <wens@csie.org>11 - Maxime Ripard <mripard@kernel.org>14 "#gpio-cells":21 "#interrupt-cells":30 - allwinner,sun4i-a10-pinctrl31 - allwinner,sun5i-a10s-pinctrl[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>48 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>51 interrupt-parent = <&gic>;52 #address-cells = <1>;53 #size-cells = <1>;56 #address-cells = <1>;[all …]
6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>48 #include <dt-bindings/clock/sun8i-de2.h>49 #include <dt-bindings/clock/sun8i-r-ccu.h>50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>51 #include <dt-bindings/reset/sun8i-de2.h>52 #include <dt-bindings/reset/sun8i-r-ccu.h>53 #include <dt-bindings/thermal/thermal.h>56 interrupt-parent = <&gic>;[all …]
2 * Copyright 2014 Chen-Yu Tsai4 * Chen-Yu Tsai <wens@csie.org>6 * This file is dual-licensed: you can use it either under the terms45 #include <dt-bindings/interrupt-controller/arm-gic.h>47 #include <dt-bindings/clock/sun9i-a80-ccu.h>48 #include <dt-bindings/clock/sun9i-a80-de.h>49 #include <dt-bindings/clock/sun9i-a80-usb.h>50 #include <dt-bindings/reset/sun9i-a80-ccu.h>51 #include <dt-bindings/reset/sun9i-a80-de.h>52 #include <dt-bindings/reset/sun9i-a80-usb.h>[all …]
1 // SPDX-License-Identifier: GPL-2.0+4 * found on Allwinner A23, A31s, A33, H3 and A64 Socs6 * Copyright 2016 Chen-Yu Tsai <wens@csie.org>15 #include "sun8i-adda-pr-regmap.h"18 #define ADDA_PR 0x0 /* PRCM base + 0x1c0 */34 /* De-assert reset */ in adda_reg_read()57 /* De-assert reset */ in adda_reg_write()82 .name = "adda-pr",102 MODULE_ALIAS("platform:sunxi-adda-pr");
4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM6412 ---help---24 ---help---26 as the original A10 (mach-sun4i).30 ---help---37 ---help---40 not have official open-source DRAM initialization code, but can46 ---help---48 have only 16-bit memory buswidth.52 ---help---[all …]
2 * Sun8i platform dram controller init.6 * SPDX-License-Identifier: GPL-2.0+16 * The register-layout of the sunxi_mctl_phy_reg-s looks a lot like the one19 * "Table4-2 DDR3 PHY Registers"28 #include <asm/arch/prcm.h>42 /* tpr0 - 10 contain timing constants or-ed together in u32 vals */69 setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()72 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()103 writel(0x40b, &mctl_phy->dcr); in mctl_init()105 writel(0x1000040b, &mctl_phy->dcr); in mctl_init()[all …]
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