1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * This driver provides regmap to access to analog part of audio codec
4*4882a593Smuzhiyun * found on Allwinner A23, A31s, A33, H3 and A64 Socs
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
7*4882a593Smuzhiyun * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/regmap.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "sun8i-adda-pr-regmap.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* Analog control register access bits */
18*4882a593Smuzhiyun #define ADDA_PR 0x0 /* PRCM base + 0x1c0 */
19*4882a593Smuzhiyun #define ADDA_PR_RESET BIT(28)
20*4882a593Smuzhiyun #define ADDA_PR_WRITE BIT(24)
21*4882a593Smuzhiyun #define ADDA_PR_ADDR_SHIFT 16
22*4882a593Smuzhiyun #define ADDA_PR_ADDR_MASK GENMASK(4, 0)
23*4882a593Smuzhiyun #define ADDA_PR_DATA_IN_SHIFT 8
24*4882a593Smuzhiyun #define ADDA_PR_DATA_IN_MASK GENMASK(7, 0)
25*4882a593Smuzhiyun #define ADDA_PR_DATA_OUT_SHIFT 0
26*4882a593Smuzhiyun #define ADDA_PR_DATA_OUT_MASK GENMASK(7, 0)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* regmap access bits */
adda_reg_read(void * context,unsigned int reg,unsigned int * val)29*4882a593Smuzhiyun static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun void __iomem *base = (void __iomem *)context;
32*4882a593Smuzhiyun u32 tmp;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* De-assert reset */
35*4882a593Smuzhiyun writel(readl(base) | ADDA_PR_RESET, base);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Clear write bit */
38*4882a593Smuzhiyun writel(readl(base) & ~ADDA_PR_WRITE, base);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun /* Set register address */
41*4882a593Smuzhiyun tmp = readl(base);
42*4882a593Smuzhiyun tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
43*4882a593Smuzhiyun tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
44*4882a593Smuzhiyun writel(tmp, base);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Read back value */
47*4882a593Smuzhiyun *val = readl(base) & ADDA_PR_DATA_OUT_MASK;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun return 0;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
adda_reg_write(void * context,unsigned int reg,unsigned int val)52*4882a593Smuzhiyun static int adda_reg_write(void *context, unsigned int reg, unsigned int val)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun void __iomem *base = (void __iomem *)context;
55*4882a593Smuzhiyun u32 tmp;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* De-assert reset */
58*4882a593Smuzhiyun writel(readl(base) | ADDA_PR_RESET, base);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Set register address */
61*4882a593Smuzhiyun tmp = readl(base);
62*4882a593Smuzhiyun tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);
63*4882a593Smuzhiyun tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;
64*4882a593Smuzhiyun writel(tmp, base);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* Set data to write */
67*4882a593Smuzhiyun tmp = readl(base);
68*4882a593Smuzhiyun tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);
69*4882a593Smuzhiyun tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;
70*4882a593Smuzhiyun writel(tmp, base);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Set write bit to signal a write */
73*4882a593Smuzhiyun writel(readl(base) | ADDA_PR_WRITE, base);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Clear write bit */
76*4882a593Smuzhiyun writel(readl(base) & ~ADDA_PR_WRITE, base);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct regmap_config adda_pr_regmap_cfg = {
82*4882a593Smuzhiyun .name = "adda-pr",
83*4882a593Smuzhiyun .reg_bits = 5,
84*4882a593Smuzhiyun .reg_stride = 1,
85*4882a593Smuzhiyun .val_bits = 8,
86*4882a593Smuzhiyun .reg_read = adda_reg_read,
87*4882a593Smuzhiyun .reg_write = adda_reg_write,
88*4882a593Smuzhiyun .fast_io = true,
89*4882a593Smuzhiyun .max_register = 31,
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
sun8i_adda_pr_regmap_init(struct device * dev,void __iomem * base)92*4882a593Smuzhiyun struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,
93*4882a593Smuzhiyun void __iomem *base)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");
100*4882a593Smuzhiyun MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");
101*4882a593Smuzhiyun MODULE_LICENSE("GPL");
102*4882a593Smuzhiyun MODULE_ALIAS("platform:sunxi-adda-pr");
103