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Searched +full:sun4i +full:- +full:a10 +full:- +full:pll3 +full:- +full:clk (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dsun4i-a10.dtsi5 * This file is dual-licensed: you can use it either under the terms
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
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H A Dsun5i-gr8.dtsi4 * Mylène Josserand <mylene.josserand@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/clock/sun4i-a10-pll2.h>
46 #include <dt-bindings/dma/sun4i-a10.h>
47 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 interrupt-parent = <&intc>;
51 #address-cells = <1>;
52 #size-cells = <1>;
55 #address-cells = <1>;
56 #size-cells = <0>;
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H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun4i-a10-pll2.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
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H A Dsun7i-a20.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/thermal/thermal.h>
50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
51 #include <dt-bindings/dma/sun4i-a10.h>
52 #include <dt-bindings/pinctrl/sun4i-a10.h>
55 interrupt-parent = <&gic>;
62 #address-cells = <1>;
63 #size-cells = <1>;
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H A Dsun5i-a13.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
50 #include <dt-bindings/thermal/thermal.h>
53 interrupt-parent = <&intc>;
56 #address-cells = <1>;
57 #size-cells = <1>;
61 compatible = "allwinner,simple-framebuffer",
62 "simple-framebuffer";
63 allwinner,pipeline = "de_be0-lcd0";
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H A Dsun5i-a10s.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
49 #include <dt-bindings/dma/sun4i-a10.h>
50 #include <dt-bindings/pinctrl/sun4i-a10.h>
53 interrupt-parent = <&intc>;
60 #address-cells = <1>;
61 #size-cells = <1>;
65 compatible = "allwinner,simple-framebuffer",
66 "simple-framebuffer";
67 allwinner,pipeline = "de_be0-lcd0-hdmi";
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H A Dsun9i-a80.dtsi2 * Copyright 2014 Chen-Yu Tsai
4 * Chen-Yu Tsai <wens@csie.org>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&gic>;
55 #address-cells = <1>;
56 #size-cells = <0>;
59 compatible = "arm,cortex-a7";
65 compatible = "arm,cortex-a7";
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dallwinner,sun4i-a10-pll3-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll3-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Video PLL Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
20 const: allwinner,sun4i-a10-pll3-clk
28 clock-output-names:
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H A Dallwinner,sun4i-a10-tcon-ch0-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-tcon-ch0-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 TCON Channel 0 Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 "#reset-cells":
24 - allwinner,sun4i-a10-tcon-ch0-clk
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H A Dallwinner,sun4i-a10-display-clk.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-display-clk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Clock Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 "#clock-cells":
19 "#reset-cells":
23 const: allwinner,sun4i-a10-display-clk
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H A Dfixed-factor-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
25 clock-div:
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for sunxi specific clk
6 obj-$(CONFIG_CLK_SUNXI) += clk-factors.o
8 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-sunxi.o
9 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-codec.o
10 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-hosc.o
11 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-mod1.o
12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
13 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-ve.o
14 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a20-gmac.o
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H A Dclk-sun4i-pll3.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
23 const char *clk_name = node->name, *parent; in sun4i_a10_pll3_setup()
28 struct clk *clk; in sun4i_a10_pll3_setup() local
31 of_property_read_string(node, "clock-output-names", &clk_name); in sun4i_a10_pll3_setup()
44 gate->reg = reg; in sun4i_a10_pll3_setup()
45 gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT; in sun4i_a10_pll3_setup()
46 gate->lock = &sun4i_a10_pll3_lock; in sun4i_a10_pll3_setup()
52 mult->reg = reg; in sun4i_a10_pll3_setup()
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-fixed-factor.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
16 * prepare - clk_prepare only ensures that parents are prepared
17 * enable - clk_enable only ensures that parents are enabled
18 * rate - rate is fixed. clk->rate = parent->rate / div * mult
19 * parent - fixed parent. No clk_set_parent support
28 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
29 do_div(rate, fix->div); in clk_factor_recalc_rate()
41 best_parent = (rate / fix->mult) * fix->div; in clk_factor_round_rate()
45 return (*prate / fix->div) * fix->mult; in clk_factor_round_rate()
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