1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright 2015 Maxime Ripard
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Maxime Ripard <maxime.ripard@free-electrons.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk-provider.h>
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/spinlock.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SUN4I_A10_PLL3_GATE_BIT 31
16*4882a593Smuzhiyun #define SUN4I_A10_PLL3_DIV_WIDTH 7
17*4882a593Smuzhiyun #define SUN4I_A10_PLL3_DIV_SHIFT 0
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static DEFINE_SPINLOCK(sun4i_a10_pll3_lock);
20*4882a593Smuzhiyun
sun4i_a10_pll3_setup(struct device_node * node)21*4882a593Smuzhiyun static void __init sun4i_a10_pll3_setup(struct device_node *node)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun const char *clk_name = node->name, *parent;
24*4882a593Smuzhiyun struct clk_multiplier *mult;
25*4882a593Smuzhiyun struct clk_gate *gate;
26*4882a593Smuzhiyun struct resource res;
27*4882a593Smuzhiyun void __iomem *reg;
28*4882a593Smuzhiyun struct clk *clk;
29*4882a593Smuzhiyun int ret;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun of_property_read_string(node, "clock-output-names", &clk_name);
32*4882a593Smuzhiyun parent = of_clk_get_parent_name(node, 0);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun reg = of_io_request_and_map(node, 0, of_node_full_name(node));
35*4882a593Smuzhiyun if (IS_ERR(reg)) {
36*4882a593Smuzhiyun pr_err("%s: Could not map the clock registers\n", clk_name);
37*4882a593Smuzhiyun return;
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun gate = kzalloc(sizeof(*gate), GFP_KERNEL);
41*4882a593Smuzhiyun if (!gate)
42*4882a593Smuzhiyun goto err_unmap;
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun gate->reg = reg;
45*4882a593Smuzhiyun gate->bit_idx = SUN4I_A10_PLL3_GATE_BIT;
46*4882a593Smuzhiyun gate->lock = &sun4i_a10_pll3_lock;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun mult = kzalloc(sizeof(*mult), GFP_KERNEL);
49*4882a593Smuzhiyun if (!mult)
50*4882a593Smuzhiyun goto err_free_gate;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun mult->reg = reg;
53*4882a593Smuzhiyun mult->shift = SUN4I_A10_PLL3_DIV_SHIFT;
54*4882a593Smuzhiyun mult->width = SUN4I_A10_PLL3_DIV_WIDTH;
55*4882a593Smuzhiyun mult->lock = &sun4i_a10_pll3_lock;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun clk = clk_register_composite(NULL, clk_name,
58*4882a593Smuzhiyun &parent, 1,
59*4882a593Smuzhiyun NULL, NULL,
60*4882a593Smuzhiyun &mult->hw, &clk_multiplier_ops,
61*4882a593Smuzhiyun &gate->hw, &clk_gate_ops,
62*4882a593Smuzhiyun 0);
63*4882a593Smuzhiyun if (IS_ERR(clk)) {
64*4882a593Smuzhiyun pr_err("%s: Couldn't register the clock\n", clk_name);
65*4882a593Smuzhiyun goto err_free_mult;
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
69*4882a593Smuzhiyun if (ret) {
70*4882a593Smuzhiyun pr_err("%s: Couldn't register DT provider\n",
71*4882a593Smuzhiyun clk_name);
72*4882a593Smuzhiyun goto err_clk_unregister;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun err_clk_unregister:
78*4882a593Smuzhiyun clk_unregister_composite(clk);
79*4882a593Smuzhiyun err_free_mult:
80*4882a593Smuzhiyun kfree(mult);
81*4882a593Smuzhiyun err_free_gate:
82*4882a593Smuzhiyun kfree(gate);
83*4882a593Smuzhiyun err_unmap:
84*4882a593Smuzhiyun iounmap(reg);
85*4882a593Smuzhiyun of_address_to_resource(node, 0, &res);
86*4882a593Smuzhiyun release_mem_region(res.start, resource_size(&res));
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun CLK_OF_DECLARE(sun4i_a10_pll3, "allwinner,sun4i-a10-pll3-clk",
90*4882a593Smuzhiyun sun4i_a10_pll3_setup);
91