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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/spi/
H A Dspi-bus.txt1 SPI (Serial Peripheral Interface) busses
3 SPI busses can be described with a node for the SPI master device
4 and a set of child nodes for each SPI slave on the bus. For this
5 discussion, it is assumed that the system's SPI controller is in
6 SPI master mode. This binding does not describe SPI controllers
9 The SPI master node requires the following properties:
10 - #address-cells - number of cells required to define a chip select
11 address on the SPI bus.
12 - #size-cells - should be zero.
13 - compatible - name of SPI bus controller following generic names
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dspi-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
20 pattern: "^spi(@.*|-[0-9a-f])*$"
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H A Dicpdas-lp8841-spi-rtc.txt1 * ICP DAS LP-8841 SPI Controller for RTC
3 ICP DAS LP-8841 contains a DS-1302 RTC. RTC is connected to an IO
4 memory register, which acts as an SPI master device.
6 The device uses the standard MicroWire half-duplex transfer timing.
13 - #address-cells: should be 1
15 - #size-cells: should be 0
17 - compatible: should be "icpdas,lp8841-spi-rtc"
19 - reg: should provide IO memory address
21 Requirements to SPI slave nodes:
23 - There can be only one slave device.
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H A Dspi-bcm63xx-hsspi.txt1 Binding for Broadcom BCM6328 High Speed SPI controller
4 - compatible: must contain of "brcm,bcm6328-hsspi".
5 - reg: Base address and size of the controllers memory area.
6 - interrupts: Interrupt for the SPI block.
7 - clocks: phandles of the SPI clock and the PLL clock.
8 - clock-names: must be "hsspi", "pll".
9 - #address-cells: <1>, as required by generic SPI binding.
10 - #size-cells: <0>, also as required by generic SPI binding.
13 - num-cs: some controllers have less than 8 cs signals. Defaults to 8
16 Child nodes as per the generic SPI binding.
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H A Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SPI Controller
10 The Rockchip SPI controller is used to interface with various devices such
11 as flash and display controllers using the SPI communication interface.
14 - $ref: "spi-controller.yaml#"
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
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H A Dspi-nxp-fspi.txt4 - compatible : Should be "nxp,lx2160a-fspi"
5 "nxp,imx8qxp-fspi"
6 "nxp,imx8mm-fspi"
8 - reg : First contains the register location and length,
10 - reg-names : Should contain the resource reg names:
11 - fspi_base: configuration register address space
12 - fspi_mmap: memory mapped address space
13 - interrupts : Should contain the interrupt for the device
15 Required SPI slave node properties:
16 - reg : There are two buses (A and B) with two chip selects each.
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H A Dqcom,spi-qup.txt1 Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
6 SPI in master mode supports up to 50MHz, up to four chip selects, programmable
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
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/OK3568_Linux_fs/u-boot/arch/sandbox/include/asm/
H A Dspi.h2 * Simulate a SPI port and clients (see README.sandbox for details)
4 * Copyright (c) 2011-2013 The Chromium OS Authors.
8 * Licensed under the GPL-2 or later.
17 * The interface between the SPI bus and the SPI client. The bus will
19 * points. These should be enough for the client to emulate the SPI
27 /* The CS has been "activated" -- we won't worry about low/high */
29 /* The CS has been "deactivated" -- we won't worry about low/high */
31 /* The client is rx-ing bytes from the bus, so it should tx some */
36 * Extract the bus/cs from the spi spec and return the start of the spi
37 * client spec. If the bus/cs are invalid for the current config, then
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/rtc/
H A Depson,rx6110.txt4 The Epson RX6110 can be used with SPI or I2C busses. The kind of
8 --------
11 - compatible: should be: "epson,rx6110"
12 - reg : the I2C address of the device for I2C
21 SPI mode
22 --------
25 - compatible: should be: "epson,rx6110"
26 - reg: chip select number
27 - spi-cs-high: RX6110 needs chipselect high
28 - spi-cpha: RX6110 works with SPI shifted clock phase
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H A Dmaxim-ds1302.txt1 * Maxim/Dallas Semiconductor DS-1302 RTC
5 The device uses the standard MicroWire half-duplex transfer timing.
12 - compatible : Should be "maxim,ds1302"
14 Required SPI properties:
16 - reg : Should be address of the device chip select within
19 - spi-max-frequency : DS-1302 has 500 kHz if powered at 2.2V,
22 - spi-3wire : The device has a shared signal IN/OUT line.
24 - spi-lsb-first : DS-1302 requires least significant bit first
27 - spi-cs-high: DS-1302 has active high chip select line. This is
32 spi@901c {
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H A Dnxp,rtc-2123.txt1 NXP PCF2123 SPI Real Time Clock
4 - compatible: should be: "nxp,pcf2123"
6 - reg: should be the SPI slave chipselect address
9 - spi-cs-high: PCF2123 needs chipselect high
16 spi-cs-high;
/OK3568_Linux_fs/kernel/drivers/gpio/
H A Dgpiolib-of.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2007-2008 MontaVista Software, Inc.
24 #include "gpiolib-of.h"
27 * of_gpio_spi_cs_get_count() - special GPIO counting for SPI
33 * established "cs-gpios" for chip selects but instead rely on
35 * the counting of "cs-gpios" to count "gpios" transparent to the
40 struct device_node *np = dev->of_node; in of_gpio_spi_cs_get_count()
44 if (!con_id || strcmp(con_id, "cs")) in of_gpio_spi_cs_get_count()
46 if (!of_device_is_compatible(np, "fsl,spi") && in of_gpio_spi_cs_get_count()
48 !of_device_is_compatible(np, "ibm,ppc4xx-spi")) in of_gpio_spi_cs_get_count()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-ppc4xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SPI_PPC4XX SPI controller driver.
9 * Based in part on drivers/spi/spi_s3c24xx.c
17 * The PPC4xx SPI controller has no FIFO so each sent/received byte will
18 * generate an interrupt to the CPU. This can cause high CPU utilization.
20 * during SPI transfers by setting max_speed_hz via the device tree.
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
39 #include <asm/dcr-regs.h>
41 /* bits in mode register - bit 0 is MSb */
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H A Dspi-bcm63xx-hsspi.c2 * Broadcom BCM63XX High Speed SPI Controller driver
4 * Copyright 2000-2010 Broadcom Corporation
5 * Copyright 2012-2013 Jonas Gorski <jogo@openwrt.org>
17 #include <linux/dma-mapping.h>
20 #include <linux/spi/spi.h>
97 #define HSSPI_BUS_NUM 1 /* 0 is legacy SPI */
113 static void bcm63xx_hsspi_set_cs(struct bcm63xx_hsspi *bs, unsigned int cs, in bcm63xx_hsspi_set_cs() argument
118 mutex_lock(&bs->bus_mutex); in bcm63xx_hsspi_set_cs()
119 reg = __raw_readl(bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_cs()
121 reg &= ~BIT(cs); in bcm63xx_hsspi_set_cs()
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H A Dspi-bitbang.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * polling/bitbanging SPI master controller driver utilities
15 #include <linux/spi/spi.h>
16 #include <linux/spi/spi_bitbang.h>
21 /*----------------------------------------------------------------------*/
24 * FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
25 * Use this for GPIO or shift-register level hardware APIs.
27 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
29 * used, though maybe they're called from controller-aware code.
31 * chipselect() and friends may use spi_device->controller_data and
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H A Dspi-dln2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Driver for the Diolan DLN-2 USB-SPI adapter
12 #include <linux/spi/spi.h>
19 /* SPI commands */
87 * needed because all SPI communication is serialized by the SPI core.
94 u8 cs; member
98 * Enable/Disable SPI module. The disable command will wait for transfers to
110 tx.port = dln2->port; in dln2_spi_enable()
114 len -= sizeof(tx.wait_for_completion); in dln2_spi_enable()
120 return dln2_transfer_tx(dln2->pdev, cmd, &tx, len); in dln2_spi_enable()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/
H A Dspear_spics.txt1 === ST Microelectronics SPEAr SPI CS Driver ===
4 Cell spi controller through its system registers, which otherwise remains under
7 desired by some of the device protocols above spi which expect (multiple)
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
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/OK3568_Linux_fs/u-boot/examples/standalone/
H A Drkspi.h4 * SPDX-License-Identifier: GPL-2.0+
54 SCOL_HIGH, /* Inactive state of serial clock is high */
59 CSM_HALF, /* ss_n high for half sclk_out cycles */
60 CSM_ONE, /* ss_n high for one sclk_out cycle */
80 HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
81 HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
88 FRF_SPI = 0, /* Motorola SPI */
118 #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
119 #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
122 /* SPI mode flags */
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dmotorola-cpcap.txt4 - compatible : One or both of "motorola,cpcap" or "ste,6556002"
5 - reg : SPI chip select
6 - interrupts : The interrupt line the device is connected to
7 - interrupt-controller : Marks the device node as an interrupt controller
8 - #interrupt-cells : The number of cells to describe an IRQ, should be 2
9 - #address-cells : Child device offset number of cells, should be 1
10 - #size-cells : Child device size number of cells, should be 0
11 - spi-max-frequency : Typically set to 3000000
12 - spi-cs-high : SPI chip select direction
16 The sub-functions of CPCAP get their own node with their own compatible values,
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/OK3568_Linux_fs/app/forlinx/forlinx_cmd/fltest_spidev_test/
H A Dspidev_test.c2 * SPI testing utility (using spidev driver)
11 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
22 #include <linux/spi/spidev.h>
62 pabort("can't send spi message"); in transfer()
74 printf("Usage: %s [-DsbdlHOLC3]\n", prog); in print_usage()
75 puts(" -D --device device to use (default /dev/spidev1.1)\n" in print_usage()
76 " -s --speed max speed (Hz)\n" in print_usage()
77 " -d --delay delay (usec)\n" in print_usage()
78 " -b --bpw bits per word \n" in print_usage()
79 " -l --loop loopback\n" in print_usage()
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Dspi-uclass.c4 * SPDX-License-Identifier: GPL-2.0+
11 #include <spi.h>
12 #include <dm/device-internal.h>
13 #include <dm/uclass-internal.h>
27 if (ops->set_speed) in spi_set_speed_mode()
28 ret = ops->set_speed(bus, speed); in spi_set_speed_mode()
30 ret = -EINVAL; in spi_set_speed_mode()
36 if (ops->set_mode) in spi_set_speed_mode()
37 ret = ops->set_mode(bus, mode); in spi_set_speed_mode()
39 ret = -EINVAL; in spi_set_speed_mode()
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H A Dmvebu_a3700_spi.c6 * SPDX-License-Identifier: GPL-2.0+
12 #include <spi.h>
29 /* SPI registers */
43 static void spi_cs_activate(struct spi_reg *reg, int cs) in spi_cs_activate() argument
45 setbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs); in spi_cs_activate()
48 static void spi_cs_deactivate(struct spi_reg *reg, int cs) in spi_cs_deactivate() argument
50 clrbits_le32(&reg->ctrl, MVEBU_SPI_A3700_SPI_EN_0 << cs); in spi_cs_deactivate()
54 * spi_legacy_shift_byte() - triggers the real SPI transfer
59 * This function triggers the real SPI transfer in legacy mode. It
65 * one-byte. Also, it does not guarantee that it will work if transfer
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/OK3568_Linux_fs/kernel/drivers/platform/chrome/
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
2 // SPI interface for ChromeOS Embedded Controller
14 #include <linux/spi/spi.h>
24 * about 400-500us for the EC to respond there is not a lot of
28 * SPI transfer size is 256 bytes, so at 5MHz we need a response
50 * for this, clocking in at 2-3ms.
55 * Time between raising the SPI chip select (for the end of a
64 * struct cros_ec_spi - information about a SPI-connected EC
66 * @spi: SPI device we are connected to
69 * is sent when we want to turn on CS at the start of a transaction.
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/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage.cfg5 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
12 BOOT_FROM spi # Boot from SPI flash
15 # bit 3-0: MPPSel0 2, NF_IO[2]
16 # bit 7-4: MPPSel1 2, NF_IO[3]
17 # bit 12-8: MPPSel2 2, NF_IO[4]
18 # bit 15-12: MPPSel3 2, NF_IO[5]
19 # bit 19-16: MPPSel4 1, NF_IO[6]
20 # bit 23-20: MPPSel5 1, NF_IO[7]
21 # bit 27-24: MPPSel6 1, SYSRST_O
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynqmp-ep108.dts4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
8 * SPDX-License-Identifier: GPL-2.0+
11 /dts-v1/;
14 #include "zynqmp-ep108-clk.dtsi"
32 stdout-path = "serial0:115200n8";
51 phy-handle = <&phy0>;
52 phy-mode = "rgmii-id";
55 max-speed = <100>;
65 clock-frequency = <400000>;
74 clock-frequency = <400000>;
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