1*4882a593Smuzhiyun* NXP Flex Serial Peripheral Interface (FSPI) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : Should be "nxp,lx2160a-fspi" 5*4882a593Smuzhiyun "nxp,imx8qxp-fspi" 6*4882a593Smuzhiyun "nxp,imx8mm-fspi" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun - reg : First contains the register location and length, 9*4882a593Smuzhiyun Second contains the memory mapping address and length 10*4882a593Smuzhiyun - reg-names : Should contain the resource reg names: 11*4882a593Smuzhiyun - fspi_base: configuration register address space 12*4882a593Smuzhiyun - fspi_mmap: memory mapped address space 13*4882a593Smuzhiyun - interrupts : Should contain the interrupt for the device 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired SPI slave node properties: 16*4882a593Smuzhiyun - reg : There are two buses (A and B) with two chip selects each. 17*4882a593Smuzhiyun This encodes to which bus and CS the flash is connected: 18*4882a593Smuzhiyun - <0>: Bus A, CS 0 19*4882a593Smuzhiyun - <1>: Bus A, CS 1 20*4882a593Smuzhiyun - <2>: Bus B, CS 0 21*4882a593Smuzhiyun - <3>: Bus B, CS 1 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample showing the usage of two SPI NOR slave devices on bus A: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyunfspi0: spi@20c0000 { 26*4882a593Smuzhiyun compatible = "nxp,lx2160a-fspi"; 27*4882a593Smuzhiyun reg = <0x0 0x20c0000 0x0 0x10000>, <0x0 0x20000000 0x0 0x10000000>; 28*4882a593Smuzhiyun reg-names = "fspi_base", "fspi_mmap"; 29*4882a593Smuzhiyun interrupts = <0 25 0x4>; /* Level high type */ 30*4882a593Smuzhiyun clocks = <&clockgen 4 3>, <&clockgen 4 3>; 31*4882a593Smuzhiyun clock-names = "fspi_en", "fspi"; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun mt35xu512aba0: flash@0 { 34*4882a593Smuzhiyun reg = <0>; 35*4882a593Smuzhiyun .... 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun mt35xu512aba1: flash@1 { 39*4882a593Smuzhiyun reg = <1>; 40*4882a593Smuzhiyun .... 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun}; 43