1*4882a593Smuzhiyun=== ST Microelectronics SPEAr SPI CS Driver === 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSPEAr platform provides a provision to control chipselects of ARM PL022 Prime 4*4882a593SmuzhiyunCell spi controller through its system registers, which otherwise remains under 5*4882a593SmuzhiyunPL022 control. If chipselect remain under PL022 control then they would be 6*4882a593Smuzhiyunreleased as soon as transfer is over and TxFIFO becomes empty. This is not 7*4882a593Smuzhiyundesired by some of the device protocols above spi which expect (multiple) 8*4882a593Smuzhiyuntransfers without releasing their chipselects. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunChipselects can be controlled by software by turning them as GPIOs. SPEAr 11*4882a593Smuzhiyunprovides another interface through system registers through which software can 12*4882a593Smuzhiyundirectly control each PL022 chipselect. Hence, it is natural for SPEAr to export 13*4882a593Smuzhiyunthe control of this interface as gpio. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired properties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun * compatible: should be defined as "st,spear-spics-gpio" 18*4882a593Smuzhiyun * reg: mentioning address range of spics controller 19*4882a593Smuzhiyun * st-spics,peripcfg-reg: peripheral configuration register offset 20*4882a593Smuzhiyun * st-spics,sw-enable-bit: bit offset to enable sw control 21*4882a593Smuzhiyun * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22*4882a593Smuzhiyun * st-spics,cs-enable-mask: chip select number bit mask 23*4882a593Smuzhiyun * st-spics,cs-enable-shift: chip select number program offset 24*4882a593Smuzhiyun * gpio-controller: Marks the device node as gpio controller 25*4882a593Smuzhiyun * #gpio-cells: should be 1 and will mention chip select number 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunAll the above bit offsets are within peripcfg register. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun------- 31*4882a593Smuzhiyunspics: spics@e0700000{ 32*4882a593Smuzhiyun compatible = "st,spear-spics-gpio"; 33*4882a593Smuzhiyun reg = <0xe0700000 0x1000>; 34*4882a593Smuzhiyun st-spics,peripcfg-reg = <0x3b0>; 35*4882a593Smuzhiyun st-spics,sw-enable-bit = <12>; 36*4882a593Smuzhiyun st-spics,cs-value-bit = <11>; 37*4882a593Smuzhiyun st-spics,cs-enable-mask = <3>; 38*4882a593Smuzhiyun st-spics,cs-enable-shift = <8>; 39*4882a593Smuzhiyun gpio-controller; 40*4882a593Smuzhiyun #gpio-cells = <2>; 41*4882a593Smuzhiyun}; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593Smuzhiyunspi0: spi@e0100000 { 45*4882a593Smuzhiyun num-cs = <3>; 46*4882a593Smuzhiyun cs-gpios = <&gpio1 7 0>, <&spics 0>, 47*4882a593Smuzhiyun <&spics 1>; 48*4882a593Smuzhiyun ... 49*4882a593Smuzhiyun} 50