Home
last modified time | relevance | path

Searched +full:dsi +full:- +full:rx (Results 1 – 25 of 129) sorted by relevance

123456

/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
35 /* DSI D-PHY Layer Registers */
37 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
50 /* DSI PPI Layer Registers */
[all …]
H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
33 #include "nwl-dsi.h"
35 #define DRV_NAME "nwl-dsi"
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
89 * DSI data
91 * TODO: Since panel_bridges do their DSI setup in enable we
[all …]
H A Dcdns-dsi.c1 // SPDX-License-Identifier: GPL-2.0
27 #include <linux/phy/phy-mipi-dphy.h>
71 #define DATA_LANE_EN(x) BIT((x) - 1)
488 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
490 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
502 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
507 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
512 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
519 if (output->dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in cdns_dsi_mode2cfg()
522 bpp = mipi_dsi_pixel_format_to_bpp(output->dev->format); in cdns_dsi_mode2cfg()
[all …]
H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
28 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
42 /* DSI layer registers */
43 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
125 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
126 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
129 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
136 /* Lane enable PPI and DSI register bits */
164 int ret = ctx->error; in tc358764_clear_error()
166 ctx->error = 0; in tc358764_clear_error()
[all …]
H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
15 #include <sound/hdmi-codec.h>
116 { 0x8106, 0x40 }, /* port A rx current */ in lt9611_mipi_input_analog()
119 { 0x8111, 0x40 }, /* port B rx current */ in lt9611_mipi_input_analog()
123 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
124 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
127 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
142 if (mode->hdisplay == 3840) in lt9611_mipi_input_digital()
145 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/include/mach/
H A Dmipi_dsim.h7 * SPDX-License-Identifier: GPL-2.0+
63 /* MIPI DSI Processor-to-Peripheral transaction types */
112 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
122 * In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
123 * start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
127 * if this variable is set, DSI master ignores HFP area in VIDEO mode.
130 * if this variable is set, DSI master ignores HBP area in VIDEO mode.
133 * if this variable is set, DSI master ignores HSA area in VIDEO mode.
140 * in Non-burst mode, RGB data area is filled with RGB data and NULL
155 * BTA requests to D-PHY automatically. this counter value specifies
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dmdfld_dsi_pkg_sender.c48 "RX SOT Error",
49 "RX SOT Sync Error",
50 "RX EOT Sync Error",
51 "RX Escape Mode Entry Error",
52 "RX LP TX Sync Error",
53 "RX HS Receive Timeout Error",
54 "RX False Control Error",
55 "RX ECC Single Bit Error",
56 "RX ECC Multibit Error",
57 "RX Checksum Error",
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c36 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
37 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
38 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
39 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
42 /* Get DSI clock from pixel clock */
49 /* DSI data rate = pixel clock * bits per pixel / lane count in dsi_clk_from_pclk()
67 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); in dsi_calc_mnp()
68 return -ECHRNG; in dsi_calc_mnp()
85 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); in dsi_calc_mnp()
91 * +/- the required clock in dsi_calc_mnp()
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/video/
H A Dexynos_mipi_dsi.txt1 Exynos MIPI-DSIM Controller
6 compatible: should be "samsung,exynos-mipi-dsi"
7 reg: Base address of MIPI-DSIM IP.
10 samsung,dsim-config-e-interface: interface to be used (RGB interface
12 samsung,dsim-config-e-virtual-ch: virtual channel number that main
14 samsung,dsim-config-e-pixel-format: pixel stream format for main
16 samsung,dsim-config-e-burst-mode: selects Burst mode in Video mode.
17 in Non-burst mode, RGB data area is filled with RGB data and
19 samsung,dsim-config-e-no-data-lane: data lane count used by Master.
20 samsung,dsim-config-e-byte-clk: select byte clock source.
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/mfd/dbx500-prcmu.h>
9 #include <dt-bindings/arm/ux500_pm_domains.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
37 #address-cells = <1>;
[all …]
H A Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dstm32mp157c-ev1.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
6 /dts-v1/;
8 #include "stm32mp157c-ed1.dts"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
14 compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
17 stdout-path = "serial0:115200n8";
27 clk_ext_camera: clk-ext-camera {
28 #clock-cells = <0>;
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra114.dtsi1 #include <dt-bindings/clock/tegra114-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra114-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 interrupt-parent = <&lic>;
14 compatible = "nvidia,tegra114-host1x", "simple-bus";
20 reset-names = "host1x";
22 #address-cells = <1>;
23 #size-cells = <1>;
[all …]
H A Dtegra210.dtsi1 #include <dt-bindings/clock/tegra210-car.h>
2 #include <dt-bindings/gpio/tegra-gpio.h>
3 #include <dt-bindings/memory/tegra210-mc.h>
4 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
10 interrupt-parent = <&lic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
14 pcie-controller@01003000 {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/bridge/
H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge bindings
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridge TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
30 vdd-supply:
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
24 #include "dsi.h"
25 #include "dsi.xml.h"
37 return -EINVAL; in dsi_get_version()
41 * makes all other registers 4-byte shifted down. in dsi_get_version()
45 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In in dsi_get_version()
52 /* older dsi host, there is no register shift */ in dsi_get_version()
60 return -EINVAL; in dsi_get_version()
76 return -EINVAL; in dsi_get_version()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/exynos/
H A Dexynos_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC MIPI DSI Master driver.
104 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
105 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
321 static inline void exynos_dsi_write(struct exynos_dsi *dsi, enum reg_idx idx, in exynos_dsi_write() argument
325 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_write()
328 static inline u32 exynos_dsi_read(struct exynos_dsi *dsi, enum reg_idx idx) in exynos_dsi_read() argument
330 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in exynos_dsi_read()
510 { .compatible = "samsung,exynos3250-mipi-dsi",
512 { .compatible = "samsung,exynos4210-mipi-dsi",
[all …]
/OK3568_Linux_fs/kernel/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/mcde/
H A Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
89 dev_err(d->dev, "direct command read ERR received\n"); in mcde_dsi_irq()
[all …]
/OK3568_Linux_fs/u-boot/drivers/video/exynos/
H A Dexynos_mipi_dsi.c7 * SPDX-License-Identifier: GPL-2.0+
25 #define master_to_driver(a) (a->dsim_lcd_drv)
26 #define master_to_device(a) (a->dsim_lcd_dev)
46 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
49 if (!lcd_dev->name) { in exynos_mipi_dsi_register_lcd_device()
51 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
57 return -EFAULT; in exynos_mipi_dsi_register_lcd_device()
60 dsim_ddi->dsim_lcd_dev = lcd_dev; in exynos_mipi_dsi_register_lcd_device()
62 list_add_tail(&dsim_ddi->list, &dsim_ddi_list); in exynos_mipi_dsi_register_lcd_device()
74 lcd_dev = dsim_ddi->dsim_lcd_dev; in exynos_mipi_dsi_find_lcd_device()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/omapdrm/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
111 #define REG_GET(dsi, idx, start, end) \ argument
112 FLD_GET(dsi_read_reg(dsi, idx), start, end)
114 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
207 static int dsi_display_init_dispc(struct dsi_data *dsi);
208 static void dsi_display_uninit_dispc(struct dsi_data *dsi);
210 static int dsi_vc_send_null(struct dsi_data *dsi, int channel);
[all …]
/OK3568_Linux_fs/kernel/drivers/misc/rk628/
H A Drk628_dsi.c1 // SPDX-License-Identifier: GPL-2.0
5 * Author: Guochun Huang <hero.huang@rock-chips.com>
16 /* Test Code: 0x44 (HS RX Control of Lane 0) */
46 /* MIPI DSI Processor-to-Peripheral transaction types */
97 /* MIPI DSI Peripheral-to-Processor transaction types */
164 * struct mipi_dsi_msg - read/write DSI buffer
186 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
200 static inline int dsi_write(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_write() argument
205 dsi_base = dsi->id ? DSI1_BASE : DSI0_BASE; in dsi_write()
210 static inline int dsi_read(struct rk628 *rk628, const struct rk628_dsi *dsi, in dsi_read() argument
[all …]

123456