Home
last modified time | relevance | path

Searched +full:12 +full:- +full:bit (Results 1 – 25 of 1140) sorted by relevance

12345678910>>...46

/OK3568_Linux_fs/kernel/drivers/net/dsa/
H A Dmv88e6060.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
17 #define PORT_STATUS_PAUSE_EN BIT(15)
18 #define PORT_STATUS_MY_PAUSE BIT(14)
20 #define PORT_STATUS_RESOLVED BIT(13)
21 #define PORT_STATUS_LINK BIT(12)
22 #define PORT_STATUS_PORTMODE BIT(11)
23 #define PORT_STATUS_PHYMODE BIT(10)
24 #define PORT_STATUS_DUPLEX BIT(9)
25 #define PORT_STATUS_SPEED BIT(8)
[all …]
/OK3568_Linux_fs/u-boot/board/keymile/km_arm/
H A Dkwbimage_128M16_1.cfg10 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
H A Dkwbimage_256M8_1.cfg7 # SPDX-License-Identifier: GPL-2.0+
9 # Refer doc/README.kwbimage for more details about how-to configure
12 # This configuration applies to COGE5 design (ARM-part)
13 # Two 8-Bit devices are connected on the 16-Bit bus on the same
14 # chip-select. The supported devices are
15 # MT47H256M8EB-3IT:C
16 # MT47H256M8EB-25EIT:C
22 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
23 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
24 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
/OK3568_Linux_fs/kernel/sound/firewire/bebob/
H A Dbebob_command.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * bebob_command.c - driver for BeBoB based devices
5 * Copyright (c) 2013-2014 Takashi Sakamoto
16 buf = kzalloc(12, GFP_KERNEL); in avc_audio_set_selector()
18 return -ENOMEM; in avc_audio_set_selector()
30 err = fcp_avc_transaction(unit, buf, 12, buf, 12, in avc_audio_set_selector()
31 BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | in avc_audio_set_selector()
32 BIT(6) | BIT(7) | BIT(8)); in avc_audio_set_selector()
36 err = -EIO; in avc_audio_set_selector()
38 err = -ENOSYS; in avc_audio_set_selector()
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/realtek/rtw88/
H A Drtw8821c.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
21 ether_addr_copy(efuse->addr, map->e.mac_addr); in rtw8821ce_efuse_parsing()
26 struct rtw_efuse *efuse = &rtwdev->efuse; in rtw8821c_read_efuse()
32 efuse->rfe_option = map->rfe_option; in rtw8821c_read_efuse()
33 efuse->rf_board_option = map->rf_board_option; in rtw8821c_read_efuse()
34 efuse->crystal_cap = map->xtal_k; in rtw8821c_read_efuse()
35 efuse->pa_type_2g = map->pa_type; in rtw8821c_read_efuse()
36 efuse->pa_type_5g = map->pa_type; in rtw8821c_read_efuse()
37 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
[all …]
/OK3568_Linux_fs/kernel/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
[all …]
H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
19 #define ANA_ANAGEFIL_VID_VAL(x) ((x) & GENMASK(12, 0))
20 #define ANA_ANAGEFIL_VID_VAL_M GENMASK(12, 0)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/include/asm/
H A Dsysreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
20 * [20-19] : Op0
21 * [18-16] : Op1
22 * [15-12] : CRn
23 * [11-8] : CRm
24 * [7-5] : Op2
30 #define CRn_shift 12
81 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
238 #define SYS_PAR_EL1_F BIT(0)
[all …]
/OK3568_Linux_fs/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3308.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
22 .route_val = BIT(16 + 0) | BIT(0),
29 .route_val = BIT(16 + 2) | BIT(16 + 3),
36 .route_val = BIT(16 + 2) | BIT(16 + 3) | BIT(2),
43 .route_val = BIT(16 + 4),
47 .pin = 12,
50 .route_val = BIT(16 + 4) | BIT(4),
52 /* i2s-8ch-1-sclktxm0 */
57 .route_val = BIT(16 + 3),
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/comedi/drivers/
H A Dni_stc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Register descriptions for NI DAQ-STC chip
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1998-9 David A. Schleef <ds@schleef.org>
11 * DAQ-STC Technical Reference Manual
21 * Registers in the National Instruments DAQ-STC chip
25 #define NISTC_INTA_ACK_G0_GATE BIT(15)
26 #define NISTC_INTA_ACK_G0_TC BIT(14)
27 #define NISTC_INTA_ACK_AI_ERR BIT(13)
28 #define NISTC_INTA_ACK_AI_STOP BIT(12)
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/i2c/
H A Dtda1997x.txt1 Device-Tree bindings for the NXP TDA1997x HDMI receiver
6 - RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
7 - YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
8 - YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
9 - YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
10 - YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
11 - YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
12 - YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
13 - YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
16 - RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
[all …]
/OK3568_Linux_fs/kernel/drivers/soc/mediatek/
H A Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
26 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
27 #define MTK_SCPD_FWAIT_SRAM BIT(1)
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/tve200/
H A Dtve200_drm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2006-2008 Intel Corporation
28 /* Bits 2-31 are valid physical base addresses */
36 #define TVE200_INT_BUS_ERR BIT(7)
37 #define TVE200_INT_V_STATUS BIT(6) /* vertical blank */
38 #define TVE200_INT_V_NEXT_FRAME BIT(5)
39 #define TVE200_INT_U_NEXT_FRAME BIT(4)
40 #define TVE200_INT_Y_NEXT_FRAME BIT(3)
41 #define TVE200_INT_V_FIFO_UNDERRUN BIT(2)
42 #define TVE200_INT_U_FIFO_UNDERRUN BIT(1)
[all …]
/OK3568_Linux_fs/kernel/include/linux/mfd/
H A Dwl1273-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * include/linux/mfd/wl1273-core.h
17 #define WL1273_FM_DRIVER_NAME "wl1273-fm"
28 #define WL1273_MOST_MODE_SET 12
125 #define WL1273_MODE_RX BIT(0)
126 #define WL1273_MODE_TX BIT(1)
127 #define WL1273_MODE_OFF BIT(2)
128 #define WL1273_MODE_SUSPENDED BIT(3)
130 #define WL1273_RADIO_CHILD BIT(0)
131 #define WL1273_CODEC_CHILD BIT(1)
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
35 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)
36 # define V3D_IDENT1_TUPS_SHIFT 12
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8723ds/include/
H A Drtl8812a_xmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
22 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
23 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
26 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
27 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
38 #define BMC BIT(24)
39 #define LSG BIT(26)
40 #define FSG BIT(27)
41 #define OWN BIT(31)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8189fs/include/
H A Drtl8812a_xmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
22 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
23 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
26 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
27 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
38 #define BMC BIT(24)
39 #define LSG BIT(26)
40 #define FSG BIT(27)
41 #define OWN BIT(31)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188fu/include/
H A Drtl8812a_xmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
22 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
23 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
26 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
27 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
38 #define BMC BIT(24)
39 #define LSG BIT(26)
40 #define FSG BIT(27)
41 #define OWN BIT(31)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8821cs/include/
H A Drtl8812a_xmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
22 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
23 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
26 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
27 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
38 #define BMC BIT(24)
39 #define LSG BIT(26)
40 #define FSG BIT(27)
41 #define OWN BIT(31)
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rtl8188eu/include/
H A Drtl8812a_xmit.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2017 Realtek Corporation.
22 #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
23 #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
26 #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
27 #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
38 #define BMC BIT(24)
39 #define LSG BIT(26)
40 #define FSG BIT(27)
41 #define OWN BIT(31)
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h36 //H2CPKT - CAT(TEST)
48 // CLASS 0 - CMD_PATH
51 // CLASS 1 - SND_Test
53 // CLASS 2 - PLATFORM_AUTO_TEST
70 // CLASS 3 - MAC_TEST
73 // CLASS 4 - FW_AUTO_TEST
77 // CLASS 5 - FW_STATUS_TEST
81 //H2CPKT - CAT(MAC)
107 // CLASS 0 - FW_INFO
114 // CLASS 1 - WOW
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/hal_g6/mac/fw_ax/inc_hdr/
H A Dfwcmd_intf.h36 //H2CPKT - CAT(TEST)
48 // CLASS 0 - CMD_PATH
51 // CLASS 1 - SND_Test
53 // CLASS 2 - PLATFORM_AUTO_TEST
70 // CLASS 3 - MAC_TEST
73 // CLASS 4 - FW_AUTO_TEST
77 // CLASS 5 - FW_STATUS_TEST
81 //H2CPKT - CAT(MAC)
107 // CLASS 0 - FW_INFO
114 // CLASS 1 - WOW
[all …]
/OK3568_Linux_fs/kernel/drivers/media/platform/omap3isp/
H A Dispreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
50 #define ISPCCP2_SYSCONFIG_MSTANDBY_MODE_SHIFT 12
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
[all …]

12345678910>>...46